<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE language SYSTEM "language.dtd">
<language name="Verilog" version="4" kateversion="2.4" section="Hardware" extensions="*.v;*.V;*.vl" mimetype="text/x-verilog-src" author="Yevgen Voronenko (ysv22@drexel.edu), Ryan Dalzell (ryan@tullyroan.com)" license="">
  <highlighting>
    <list name="keywords">
      <item>macromodule</item>
      <item>table</item>
      <item>endtable</item>
      <item>specify</item>
      <item>specparam</item>
      <item>endspecify</item>

      <item>defparam</item>
      <item>default</item>
      <item>if</item>
      <item>ifnone</item>
      <item>else</item>
      <item>forever</item>
      <item>while</item>
      <item>for</item>
      <item>wait</item>
      <item>repeat</item>
      <item>disable</item>

      <item>assign</item>
      <item>deassign</item>
      <item>force</item>
      <item>release</item>

      <item>always</item>
      <item>initial</item>
      <item>edge</item>
      <item>posedge</item>
      <item>negedge</item>

      <!-- verilog-2001 keywords -->
      <item>config</item>
      <item>endconfig</item>
      <item>library</item>
      <item>design</item>
      <item>liblist</item>
      <item>cell</item>
      <item>use</item>
      <item>instance</item>
    </list>

    <list name="beginwords">
        <item>begin</item>
        <item>fork</item>
        <item>module</item>
        <item>case</item>
        <item>casex</item>
        <item>casez</item>
        <item>task</item>
        <item>function</item>
        <item>generate</item>
    </list>

    <list name="endwords">
        <item>end</item>
        <item>join</item>
        <item>endmodule</item>
        <item>endcase</item>
        <item>endtask</item>
        <item>endfunction</item>
        <item>endgenerate</item>
    </list>

    <list name="strength">
	<!-- drive strength supply0/supply1 omitted, its in types.. -->
	<item>strong0</item>
	<item>strong1</item>
	<item>pull0</item>
	<item>pull1</item>
	<item>weak0</item>
	<item>weak1</item>
	<item>highz0</item>
	<item>highz1</item>
	<!-- charge strength -->
	<item>small</item>
	<item>medium</item>
	<item>large</item>
    </list>

    <list name="gates">
       <item>pullup</item>
       <item>pulldown</item>
       <item>cmos</item>
       <item>rcmos</item>
       <item>nmos</item>
       <item>pmos</item>
       <item>rnmos</item>
       <item>rpmos</item>
       <item>and</item>
       <item>nand</item>
       <item>or</item>
       <item>nor</item>
       <item>xor</item>
       <item>xnor</item>
       <item>not</item>
       <item>buf</item>
       <item>tran</item>
       <item>rtran</item>
       <item>tranif0</item>
       <item>tranif1</item>
       <item>rtranif0</item>
       <item>rtranif1</item>
       <item>bufif0</item>
       <item>bufif1</item>
       <item>notif0</item>
       <item>notif1</item>
    </list>

    <list name="types">
      <!-- port direction -->
      <item>input</item>
      <item>output</item>
      <item>inout</item>
      <!-- net type -->
      <item>wire</item>
      <item>tri</item>
      <item>tri0</item>
      <item>tri1</item>
      <item>wand</item>
      <item>wor</item>
      <item>triand</item>
      <item>trior</item>
      <item>supply0</item>
      <item>supply1</item>
      <!-- reg/variable -->
      <item>reg</item>
      <item>integer</item>
      <item>real</item>
      <item>realtime</item>
      <item>time</item>
      <!-- modifier -->
      <item>vectored</item>
      <item>scalared</item>
      <item>trireg</item>
      <!-- other -->
      <item>parameter</item>
      <item>event</item>
      <!-- verilog-2001 types -->
      <item>signed</item>
      <item>automatic</item>
      <item>genvar</item>
      <item>localparam</item>
    </list>

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        <keyword attribute="Keyword" String="endwords" context="#stay" endRegion="Block"/>

        <keyword attribute="Keyword" context="#stay" String="keywords" />
        <keyword attribute="Data Type" context="#stay" String="types" />
        <keyword attribute="Drive/charge strength" context="#stay" String="strength" />
        <keyword attribute="Gate instantiation" context="#stay" String="gates" />

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        <!--<RegExpr attribute="Port map" context="Port" String="\.[a-zA-Z0-9_]+"/>-->

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      </context>
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        <LineContinue attribute="String" context="Some Context"/>
        <HlCStringChar attribute="String Char" context="#stay"/>
        <DetectChar attribute="String" context="#pop" char="&quot;"/>
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        <IncludeRules context="##Alerts" />
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      <context attribute="Normal Text" lineEndContext="#pop" name="Some Context"/>

      <context attribute="Block name" lineEndContext="#pop" name="Block name">
          <DetectIdentifier attribute="Data Type" context="#pop"/>
      </context>

<!--      <context attribute="Normal Text" lineEndContext="#stay" name="Port">
          <DetectIdentifier attribute="Normal Text" context="#pop"/>
      </context>-->
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<!--       <itemData name="Port map" defStyleNum="dsDataType"/> -->
      <itemData name="Case label" defStyleNum="dsDecVal"/>
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  </highlighting>
  <general>
    <comments>
      <comment name="singleLine" start="//" />
      <comment name="multiLine" start="/*" end="*/" region="Comment"/>
    </comments>
    <keywords casesensitive="1" />
  </general>
</language>
