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<subtitle>Donated space for related uLab project
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<updated>2019-04-29T03:24:30Z</updated>
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<title>Add a several cycle "dead zone" to 7-segment decoder segment select lines to more accurately emulate real hardware</title>
<updated>2019-04-29T03:24:30Z</updated>
<author>
<name>Timothy Pearson</name>
<email>tpearson@raptorengineering.com</email>
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<published>2019-04-29T03:24:30Z</published>
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<entry>
<title>Correctly implement 7-segment display LED persistence</title>
<updated>2019-04-29T02:58:15Z</updated>
<author>
<name>Timothy Pearson</name>
<email>tpearson@raptorengineering.com</email>
</author>
<published>2019-04-29T02:58:15Z</published>
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<entry>
<title>Add user logic reset support to serial version of FPGA control interface</title>
<updated>2019-04-29T00:33:00Z</updated>
<author>
<name>Timothy Pearson</name>
<email>tpearson@raptorengineering.com</email>
</author>
<published>2019-04-29T00:33:00Z</published>
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<entry>
<title>Add intial version of Lattice remote FPGA interface</title>
<updated>2019-04-28T23:55:21Z</updated>
<author>
<name>Timothy Pearson</name>
<email>tpearson@raptorengineering.com</email>
</author>
<published>2019-04-28T23:55:21Z</published>
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Minor tweaks to core remote FPGA file to eliminate Yosys warnings and reduce design size
</content>
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<entry>
<title>Modify FPGA interface license to AGPL v3</title>
<updated>2019-04-28T22:17:19Z</updated>
<author>
<name>Timothy Pearson</name>
<email>tpearson@raptorengineering.com</email>
</author>
<published>2019-04-28T22:15:59Z</published>
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<entry>
<title>Add initial GOMC compatible uLab debug system hardware design files</title>
<updated>2014-01-10T03:16:28Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2014-01-10T03:16:28Z</published>
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