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<title>ulab/servers/fpga_server_lin/src/fpga_conn.cpp, branch master</title>
<subtitle>Donated space for related uLab project
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<updated>2019-04-29T03:40:28Z</updated>
<entry>
<title>Add options to set up control FPGA on startup and reset user FPGA on connect</title>
<updated>2019-04-29T03:40:28Z</updated>
<author>
<name>Timothy Pearson</name>
<email>tpearson@raptorengineering.com</email>
</author>
<published>2019-04-29T03:40:28Z</published>
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<entry>
<title>First pass of logic analyzer functionality (GPMC interface and server)</title>
<updated>2014-02-27T07:00:35Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2014-02-27T07:00:35Z</published>
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<entry>
<title>Hard reset user device on connection and disconnection of FPGA viewer</title>
<updated>2014-01-13T22:04:14Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2014-01-13T22:04:14Z</published>
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<id>urn:sha1:2dc576d25f02d1f65df639b0a858a03df437cfca</id>
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<entry>
<title>Lower the uLab FPGA viewer GPMC clock to reduce errors on prototype lashup</title>
<updated>2014-01-11T05:15:55Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2014-01-11T05:15:55Z</published>
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<id>urn:sha1:32b7b87d3dcd0d0f780fdfa8d5c2859bda8b175a</id>
<content type='text'>
Add memory stress tests to GPMC test program
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<entry>
<title>Add GPMC interface to FPGA server</title>
<updated>2014-01-10T08:58:09Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2014-01-10T08:58:09Z</published>
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<entry>
<title>Increase FPGA viewer refresh rate and add configuration option for same</title>
<updated>2013-10-30T17:13:05Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2013-10-30T07:24:28Z</published>
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<id>urn:sha1:b783a269490763ec242e967fa713dbf732e5ac13</id>
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</content>
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<entry>
<title>Work around data transfer problems in FTDI serial converters</title>
<updated>2013-03-04T06:16:08Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2013-03-04T06:16:08Z</published>
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<id>urn:sha1:fda60e9d28ae1a5d2bbf6fb108de89d0f6304c5a</id>
<content type='text'>
Fix glitches in FPGA viewer part
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<entry>
<title>Fix remaining name references to use the uLab system name</title>
<updated>2013-02-27T08:16:11Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2013-02-27T08:16:11Z</published>
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<id>urn:sha1:b4426c06a4374b8e1025adce41427f0b1b072721</id>
<content type='text'>
Fix incorrect Debian init scripts and a wrong binary name
</content>
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<entry>
<title>Fix FTBFS</title>
<updated>2013-02-24T05:06:56Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2013-02-24T05:06:56Z</published>
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<id>urn:sha1:fd5374f98102b3fe5988715e6c4a302c9885eb38</id>
<content type='text'>
</content>
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<entry>
<title>Add administration console</title>
<updated>2012-09-19T17:50:53Z</updated>
<author>
<name>Timothy Pearson</name>
<email>kb9vqf@pearsoncomputing.net</email>
</author>
<published>2012-09-19T17:50:53Z</published>
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