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191 lines
6.0 KiB
191 lines
6.0 KiB
/***************************************************************************
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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***************************************************************************/
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#ifndef __FPGAREGS_H__APOGEE_APN__
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#define __FPGAREGS_H__APOGEE_APN__
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#define FPGA_TOTAL_REGISTER_COUNT 103
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#define FPGA_REG_COMMAND_A 0
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#define FPGA_BIT_CMD_EXPOSE 0x0001
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#define FPGA_BIT_CMD_DARK 0x0002
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#define FPGA_BIT_CMD_TEST 0x0004
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#define FPGA_BIT_CMD_TDI 0x0008
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#define FPGA_BIT_CMD_FLUSH 0x0010
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#define FPGA_BIT_CMD_TRIGGER_EXPOSE 0x0020
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#define FPGA_REG_COMMAND_B 1
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#define FPGA_BIT_CMD_RESET 0x0002
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#define FPGA_BIT_CMD_CLEAR_ALL 0x0010
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#define FPGA_BIT_CMD_END_EXPOSURE 0x0080
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#define FPGA_BIT_CMD_RAMP_TO_SETPOINT 0x0200
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#define FPGA_BIT_CMD_RAMP_TO_AMBIENT 0x0400
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#define FPGA_BIT_CMD_START_TEMP_READ 0x2000
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#define FPGA_BIT_CMD_DAC_LOAD 0x4000
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#define FPGA_BIT_CMD_AD_CONFIG 0x8000
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#define FPGA_REG_OP_A 2
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#define FPGA_BIT_LED_DISABLE 0x0001
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#define FPGA_BIT_PAUSE_TIMER 0x0002
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#define FPGA_BIT_RATIO 0x0004
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#define FPGA_BIT_DELAY_MODE 0x0008
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#define FPGA_BIT_P_CLK_MODE 0x0010
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#define FPGA_BIT_LED_EXPOSE_DISABLE 0x0020
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#define FPGA_BIT_DISABLE_H_CLK 0x0040
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#define FPGA_BIT_SHUTTER_AMP_CONTROL 0x0080
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#define FPGA_BIT_HALT_DISABLE 0x0100
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#define FPGA_BIT_SHUTTER_MODE 0x0200
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#define FPGA_BIT_DIGITIZATION_RES 0x0400
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#define FPGA_BIT_FORCE_SHUTTER 0x0800
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#define FPGA_BIT_DISABLE_SHUTTER 0x1000
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#define FPGA_BIT_TEMP_SUSPEND 0x2000
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#define FPGA_BIT_SHUTTER_SOURCE 0x4000
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#define FPGA_BIT_TEST_MODE 0x8000
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#define FPGA_REG_OP_B 3
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#define FPGA_BIT_HCLAMP_ENABLE 0x0008
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#define FPGA_BIT_HSKIP_ENABLE 0x0010
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#define FPGA_BIT_HRAM_ENABLE 0x0020
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#define FPGA_BIT_VRAM_ENABLE 0x0040
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#define FPGA_BIT_DAC_SELECT_ZERO 0x0080
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#define FPGA_BIT_DAC_SELECT_ONE 0x0100
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#define FPGA_BIT_AD_SIMULATION 0x8000
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#define FPGA_REG_TIMER_UPPER 4
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#define FPGA_REG_TIMER_LOWER 5
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#define FPGA_REG_HRAM_INPUT 6
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#define FPGA_REG_VRAM_INPUT 7
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#define FPGA_REG_HRAM_INV_MASK 8
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#define FPGA_REG_VRAM_INV_MASK 9
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#define FPGA_REG_HCLAMP_INPUT 10
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#define FPGA_REG_HSKIP_INPUT 11
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#define FPGA_REG_PRECLAMP_SKIP_COUNT 12
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#define FPGA_REG_CLAMP_COUNT 13
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#define FPGA_REG_PREROI_SKIP_COUNT 14
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#define FPGA_REG_ROI_COUNT 15
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#define FPGA_REG_POSTROI_SKIP_COUNT 16
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#define FPGA_REG_OVERSCAN_COUNT 17
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#define FPGA_REG_IMAGE_COUNT 18
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#define FPGA_REG_VFLUSH_BINNING 19
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#define FPGA_REG_SHUTTER_CLOSE_DELAY 20
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#define FPGA_REG_POSTOVERSCAN_SKIP_COUNT 21
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#define FPGA_REG_SHUTTER_STROBE_POSITION 23
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#define FPGA_REG_SHUTTER_STROBE_PERIOD 24
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#define FPGA_REG_FAN_SPEED_CONTROL 25
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#define FPGA_REG_LED_DRIVE 26
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#define FPGA_REG_SUBSTRATE_ADJUST 27
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#define FPGA_MASK_FAN_SPEED_CONTROL 0x0FFF
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#define FPGA_MASK_LED_ILLUMINATION 0x0FFF
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#define FPGA_MASK_SUBSTRATE_ADJUST 0x0FFF
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#define FPGA_REG_TEST_COUNT_UPPER 28
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#define FPGA_REG_TEST_COUNT_LOWER 29
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#define FPGA_REG_A1_ROW_COUNT 30
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#define FPGA_REG_A1_VBINNING 31
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#define FPGA_REG_A2_ROW_COUNT 32
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#define FPGA_REG_A2_VBINNING 33
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#define FPGA_REG_A3_ROW_COUNT 34
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#define FPGA_REG_A3_VBINNING 35
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#define FPGA_MASK_VBINNING 0x0FFF
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#define FPGA_BIT_ARRAY_DIGITIZE 0x1000
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#define FPGA_BIT_ARRAY_FASTDUMP 0x4000
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#define FPGA_REG_SEQUENCE_DELAY 47
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#define FPGA_REG_TDI_RATE 48
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#define FPGA_REG_IO_PORT_WRITE 49
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#define FPGA_REG_IO_PORT_DIRECTION 50
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#define FPGA_MASK_IO_PORT_DIRECTION 0x003F
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#define FPGA_REG_IO_PORT_ASSIGNMENT 51
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#define FPGA_MASK_IO_PORT_ASSIGNMENT 0x003F
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#define FPGA_REG_LED_SELECT 52
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#define FPGA_MASK_LED_SELECT_A 0x000F
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#define FPGA_MASK_LED_SELECT_B 0x00F0
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#define FPGA_BIT_LED_EXPOSE 0x0001
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#define FPGA_BIT_LED_IMAGE_ACTIVE 0x0002
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#define FPGA_BIT_LED_FLUSHING 0x0004
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#define FPGA_BIT_LED_TRIGGER_WAIT 0x0008
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#define FPGA_BIT_LED_EXT_TRIGGER 0x0010
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#define FPGA_BIT_LED_EXT_SHUTTER_INPUT 0x0020
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#define FPGA_BIT_LED_EXT_START_READOUT 0x0040
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#define FPGA_BIT_LED_AT_TEMP 0x0080
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#define FPGA_REG_SCRATCH 53
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#define FPGA_REG_TDI_COUNT 54
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#define FPGA_REG_TEMP_DESIRED 55
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#define FPGA_REG_TEMP_RAMP_DOWN_A 57
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#define FPGA_REG_TEMP_RAMP_DOWN_B 58
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#define FPGA_REG_TEMP_BACKOFF 60
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#define FPGA_REG_TEMP_COOLER_OVERRIDE 61
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#define FPGA_MASK_TEMP_PARAMS 0x0FFF // 12 bits
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#define FPGA_REG_AD_CONFIG_DATA 62
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#define FPGA_MASK_AD_GAIN 0x07FF // 11 bits
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#define FPGA_REG_IO_PORT_READ 90
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#define FPGA_MASK_IO_PORT_DATA 0x003F
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#define FPGA_REG_GENERAL_STATUS 91
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#define FPGA_BIT_STATUS_IMAGE_EXPOSING 0x0001
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#define FPGA_BIT_STATUS_IMAGING_ACTIVE 0x0002
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#define FPGA_BIT_STATUS_DATA_HALTED 0x0004
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#define FPGA_BIT_STATUS_IMAGE_DONE 0x0008
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#define FPGA_BIT_STATUS_FLUSHING 0x0010
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#define FPGA_BIT_STATUS_WAITING_TRIGGER 0x0020
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#define FPGA_BIT_STATUS_SHUTTER_OPEN 0x0040
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#define FPGA_BIT_STATUS_PATTERN_ERROR 0x0080
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#define FPGA_BIT_STATUS_TEMP_SUSPEND_ACK 0x0100
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#define FPGA_BIT_STATUS_TEMP_REVISION 0x2000
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#define FPGA_BIT_STATUS_TEMP_AT_TEMP 0x4000
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#define FPGA_BIT_STATUS_TEMP_ACTIVE 0x8000
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#define FPGA_REG_TEMP_HEATSINK 93
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#define FPGA_REG_TEMP_CCD 94
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#define FPGA_REG_TEMP_DRIVE 95
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#define FPGA_REG_INPUT_VOLTAGE 96
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#define FPGA_MASK_INPUT_VOLTAGE 0x0FFF
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#define FPGA_REG_TEMP_REVISED 97
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#define FPGA_REG_FIFO_DATA 98
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#define FPGA_REG_FIFO_STATUS 99
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#define FPGA_REG_CAMERA_ID 100
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#define FPGA_MASK_CAMERA_ID 0x007F
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#define FPGA_REG_FIRMWARE_REV 101
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#define FPGA_REG_FIFO_FULL_COUNT 102
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#define FPGA_REG_FIFO_EMPTY_COUNT 103
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#define FPGA_REG_TDI_COUNTER 104
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#define FPGA_REG_SEQUENCE_COUNTER 105
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#endif
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