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Add initial GOMC compatible uLab debug system hardware design files

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master
Timothy Pearson 11 years ago
parent 963b88fb0b
commit 04ab7c6632
14 changed files with 1007 additions and 0 deletions
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33
fpga/gpmc/xilinx/numato/spartan6/xc6slx9/data_storage.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module data_storage(
input clka,
input [7:0] dina,
input [(RAM_ADDR_BITS-1):0] addra,
input wea,
output reg [7:0] douta);
parameter RAM_ADDR_BITS = 14;
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
always @(posedge clka) begin
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end else begin
douta <= data_storage_ram[addra];
end
end
endmodule

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module lcd_data_storage(
input clka,
input clkb,
input [7:0] dina,
input [7:0] dinb,
input [4:0] addra,
input [4:0] addrb,
input wea,
input web,
output reg [7:0] douta,
output reg [7:0] doutb);
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**5)-1:0];
always @(posedge clka) begin
douta <= data_storage_ram[addra];
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end
end
always @(posedge clkb) begin
doutb <= data_storage_ram[addrb];
if (web) begin
data_storage_ram[addrb] <= dinb;
doutb <= dinb;
end
end
endmodule

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
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# (c) 2013 Timothy Pearson, Raptor Engineering
# Released into the Public Domain
NET "clk" LOC = "V10" |IOSTANDARD = "LVCMOS33";
TIMESPEC TS_clk = PERIOD "clk" 100000 KHz HIGH 50%;
#NET "serial_input" LOC = "T12" | IOSTANDARD = "LVCMOS33";
#NET "serial_output" LOC = "M10" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "gpmc_advn" LOC = "C5" |IOSTANDARD = "LVCMOS33";
NET "gpmc_oen" LOC = "A3" |IOSTANDARD = "LVCMOS33";
NET "gpmc_wen" LOC = "A5" |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<0>" LOC = "A6" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<1>" LOC = "C8" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<2>" LOC = "C9" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<3>" LOC = "A10" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<4>" LOC = "C10" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<5>" LOC = "D9" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<6>" LOC = "D8" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_data<7>" LOC = "B6" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<0>" LOC = "A11" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<1>" LOC = "F9" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<2>" LOC = "A9" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<3>" LOC = "A8" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<4>" LOC = "A7" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<5>" LOC = "C6" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<6>" LOC = "A4" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<7>" LOC = "A2" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<8>" LOC = "B11" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<9>" LOC = "G9" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<10>" LOC = "B9" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<11>" LOC = "B8" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<12>" LOC = "C7" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<13>" LOC = "D6" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<14>" LOC = "B4" |IOSTANDARD = "LVCMOS33";
NET "usermem_wen" LOC = "V16" |IOSTANDARD = "LVCMOS33";
NET "usermem_wait" LOC = "T18" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "userproc_start" LOC = "K16" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "userproc_done" LOC = "L13" |IOSTANDARD = "LVCMOS33";
NET "usermem_data<0>" LOC = "V14" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_data<1>" LOC = "T11" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_data<2>" LOC = "R11" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_data<3>" LOC = "T14" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_data<4>" LOC = "U16" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_data<5>" LOC = "T17" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_data<6>" LOC = "K15" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_data<7>" LOC = "L12" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
NET "usermem_address<0>" LOC = "K12" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<1>" LOC = "L14" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<2>" LOC = "M14" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<3>" LOC = "L15" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<4>" LOC = "N15" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<5>" LOC = "P15" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<6>" LOC = "U17" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<7>" LOC = "U13" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<8>" LOC = "V13" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<9>" LOC = "U18" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<10>" LOC = "P16" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<11>" LOC = "N16" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<12>" LOC = "L16" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<13>" LOC = "N14" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<14>" LOC = "M13" |IOSTANDARD = "LVCMOS33";
NET "four_bit_leds<0>" LOC = "G13" |IOSTANDARD = "LVCMOS33";
NET "four_bit_leds<1>" LOC = "H16" |IOSTANDARD = "LVCMOS33";
NET "four_bit_leds<2>" LOC = "G14" |IOSTANDARD = "LVCMOS33";
NET "four_bit_leds<3>" LOC = "F16" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<0>" LOC = "E18" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<1>" LOC = "C18" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<2>" LOC = "A15" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<3>" LOC = "A14" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<4>" LOC = "K14" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<5>" LOC = "H14" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<6>" LOC = "G18" |IOSTANDARD = "LVCMOS33";
NET "eight_bit_leds<7>" LOC = "F18" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<0>" LOC = "R10" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<1>" LOC = "T9" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<2>" LOC = "U7" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<3>" LOC = "R7" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<4>" LOC = "N5" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<5>" LOC = "R5" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<6>" LOC = "R3" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<7>" LOC = "T3" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<8>" LOC = "T5" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<9>" LOC = "P6" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<10>" LOC = "T7" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<11>" LOC = "V7" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<12>" LOC = "V9" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<13>" LOC = "T10" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<14>" LOC = "A12" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io<15>" LOC = "B12" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io_wen" LOC = "C11" |IOSTANDARD = "LVCMOS33";
NET "sixteen_bit_io_mode" LOC = "D11" |IOSTANDARD = "LVCMOS33";
NET "four_bit_switches<0>" LOC = "H12" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "four_bit_switches<1>" LOC = "H15" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "four_bit_switches<2>" LOC = "F14" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "four_bit_switches<3>" LOC = "F15" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<0>" LOC = "E16" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<1>" LOC = "C17" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<2>" LOC = "C15" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<3>" LOC = "B14" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<4>" LOC = "J13" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<5>" LOC = "H13" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<6>" LOC = "G16" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "eight_bit_switches<7>" LOC = "F17" |SLEW = SLOW |IOSTANDARD = "LVCMOS33";
NET "sseg_mux<0>" LOC = "U11" |IOSTANDARD = "LVCMOS33";
NET "sseg_mux<1>" LOC = "R8" |IOSTANDARD = "LVCMOS33";
NET "sseg_mux<2>" LOC = "U8" |IOSTANDARD = "LVCMOS33";
NET "sseg_mux<3>" LOC = "T6" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<0>" LOC = "U5" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<1>" LOC = "T4" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<2>" LOC = "V4" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<3>" LOC = "V5" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<4>" LOC = "V6" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<5>" LOC = "V8" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<6>" LOC = "T8" |IOSTANDARD = "LVCMOS33";
NET "sseg_data<7>" LOC = "V11" |IOSTANDARD = "LVCMOS33";
#Created by Constraints Editor (xc6slx9-csg324-3) - 2014/01/09
NET "clk" TNM_NET = clk;

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fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// uLab to ARM GPMC interface
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
// (c) 2014 Timothy Pearson
// Raptor Engineering
// http://www.raptorengineeringinc.com
//
//////////////////////////////////////////////////////////////////////////////////
module main(
input clk,
input gpmc_advn,
input gpmc_oen,
input gpmc_wen,
inout [7:0] gpmc_data,
input [RAM_ADDR_BITS:0] gpmc_address,
input usermem_wen,
output reg usermem_wait,
inout [7:0] usermem_data,
inout [RAM_ADDR_BITS:0] usermem_address,
output reg userproc_start,
input userproc_done,
input [3:0] four_bit_leds,
input [7:0] eight_bit_leds,
output reg [3:0] four_bit_switches,
output reg [7:0] eight_bit_switches,
inout [15:0] sixteen_bit_io,
input sixteen_bit_io_wen,
output reg sixteen_bit_io_mode,
input [3:0] sseg_mux,
input [7:0] sseg_data);
parameter RAM_ADDR_BITS = 14;
reg [15:0] sixteen_bit_io_in;
reg [15:0] sixteen_bit_io_out;
reg [15:0] sixteen_bit_io_reg;
reg sixteen_bit_io_wen_reg;
assign sixteen_bit_io = (sixteen_bit_io_wen) ? sixteen_bit_io_out : 16'bz;
always @(posedge clk) begin
sixteen_bit_io_reg = sixteen_bit_io;
sixteen_bit_io_wen_reg = sixteen_bit_io_wen;
if (sixteen_bit_io_wen_reg == 1'b0) begin
sixteen_bit_io_mode = 1'b1;
sixteen_bit_io_in = sixteen_bit_io_reg;
end else begin
sixteen_bit_io_mode = 1'b0;
end
end
reg [7:0] gpmc_data_out;
reg gpmc_data_driven;
assign gpmc_data = (gpmc_data_driven) ? gpmc_data_out : 8'bz;
reg [7:0] usermem_data_out;
assign usermem_data = (usermem_wen) ? usermem_data_out : 8'bz;
wire data_storage_clka;
reg [7:0] data_storage_dina;
reg [(RAM_ADDR_BITS-1):0] data_storage_addra;
reg data_storage_write_enable;
wire [7:0] data_storage_data_out;
assign data_storage_clka = clk;
data_storage #(RAM_ADDR_BITS) data_storage(.clka(data_storage_clka), .dina(data_storage_dina), .addra(data_storage_addra),
.wea(data_storage_write_enable), .douta(data_storage_data_out));
wire lcd_data_storage_clka;
wire lcd_data_storage_clkb;
reg [7:0] lcd_data_storage_dina;
reg [7:0] lcd_data_storage_dinb;
reg [4:0] lcd_data_storage_addra;
reg [4:0] lcd_data_storage_addrb;
reg lcd_data_storage_wea;
reg lcd_data_storage_web;
wire [7:0] lcd_data_storage_douta;
wire [7:0] lcd_data_storage_doutb;
assign lcd_data_storage_clka = clk;
assign lcd_data_storage_clkb = clk;
lcd_data_storage lcd_data_storage(.clka(lcd_data_storage_clka), .clkb(lcd_data_storage_clkb),
.dina(lcd_data_storage_dina), .dinb(lcd_data_storage_dinb),
.addra(lcd_data_storage_addra), .addrb(lcd_data_storage_addrb),
.wea(lcd_data_storage_wea), .web(lcd_data_storage_web),
.douta(lcd_data_storage_douta), .doutb(lcd_data_storage_doutb));
//-----------------------------------------------------------------------------------
//
// Create a 12.5MHz clock for the seven-segement LED emulator
//
//-----------------------------------------------------------------------------------
reg clk_div_by_two;
reg clk_div_by_two_oneeighty;
reg clk_div_by_four;
reg clk_div_by_eight;
reg clk_div_by_sixteen;
always @(posedge clk) begin
clk_div_by_two = !clk_div_by_two;
end
always @(negedge clk_div_by_two) begin
clk_div_by_two_oneeighty = !clk_div_by_two_oneeighty;
end
always @(posedge clk_div_by_two_oneeighty) begin
clk_div_by_four = !clk_div_by_four;
end
always @(posedge clk_div_by_four) begin
clk_div_by_eight = !clk_div_by_eight;
end
always @(posedge clk_div_by_eight) begin
clk_div_by_sixteen = !clk_div_by_sixteen;
end
//-----------------------------------------------------------------------------------
//
// Keep track of what is on the LED display
//
//-----------------------------------------------------------------------------------
reg [7:0] led_display_bytes [3:0];
reg [17:0] digit_blanker_1 = 0;
reg [17:0] digit_blanker_2 = 0;
reg [17:0] digit_blanker_3 = 0;
reg [17:0] digit_blanker_4 = 0;
reg [7:0] sseg_data_latch;
reg [3:0] sseg_mux_latch;
always @(negedge clk_div_by_sixteen) begin
sseg_data_latch = sseg_data;
sseg_mux_latch = sseg_mux;
if (sseg_mux_latch[0] == 0) begin
led_display_bytes[0] = sseg_data_latch;
digit_blanker_1 = 0;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[1] == 0) begin
led_display_bytes[1] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = 0;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[2] == 0) begin
led_display_bytes[2] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = 0;
digit_blanker_4 = digit_blanker_4 + 1;
end
if (sseg_mux_latch[3] == 0) begin
led_display_bytes[3] = sseg_data_latch;
digit_blanker_1 = digit_blanker_1 + 1;
digit_blanker_2 = digit_blanker_2 + 1;
digit_blanker_3 = digit_blanker_3 + 1;
digit_blanker_4 = 0;
end
if (digit_blanker_1 > 128000) begin
led_display_bytes[0] = 255;
end
if (digit_blanker_2 > 128000) begin
led_display_bytes[1] = 255;
end
if (digit_blanker_3 > 128000) begin
led_display_bytes[2] = 255;
end
if (digit_blanker_4 > 128000) begin
led_display_bytes[3] = 255;
end
end
//-----------------------------------------------------------------------------------
//
// Memory and register access
//
//-----------------------------------------------------------------------------------
reg gpmc_advn_reg;
reg gpmc_oen_reg;
reg gpmc_wen_reg;
reg [7:0] gpmc_data_reg;
reg [RAM_ADDR_BITS:0] gpmc_address_reg;
reg usermem_wen_reg;
reg [7:0] usermem_data_reg;
reg [RAM_ADDR_BITS:0] usermem_address_reg;
always @(posedge clk) begin
usermem_wen_reg = usermem_wen;
usermem_data_reg = usermem_data;
usermem_address_reg = usermem_address;
gpmc_advn_reg = gpmc_advn;
gpmc_oen_reg = gpmc_oen;
gpmc_wen_reg = gpmc_wen;
gpmc_data_reg = gpmc_data;
if (gpmc_advn_reg == 1'b0) begin
gpmc_address_reg = gpmc_address;
data_storage_write_enable = 1'b0;
lcd_data_storage_wea = 1'b0;
end
if (gpmc_address_reg[RAM_ADDR_BITS] == 1'b1) begin
// System memory access
usermem_wait = 1'b1;
if (gpmc_wen_reg == 1'b0) begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = gpmc_data_reg;
data_storage_write_enable = 1'b1;
end else begin
data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
gpmc_data_out = data_storage_data_out;
end
end else begin
// User memory access
usermem_wait = 1'b0;
if (usermem_address_reg[RAM_ADDR_BITS] == 1'b1) begin
// Interdevice communication region
// MEMORY MAP
// 0x20 - 0x3f: LCD data area
if (usermem_wen_reg == 1'b0) begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_dinb = usermem_data_reg;
lcd_data_storage_web = 1'b1;
end
end else begin
if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addrb = usermem_address_reg[4:0];
lcd_data_storage_web = 1'b0;
usermem_data_out = lcd_data_storage_doutb;
end else begin
// Default
usermem_data_out = 8'b00000000;
end
end
end else begin
// Client scratchpad memory area
if (usermem_wen_reg == 1'b0) begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_dina = usermem_data_reg;
data_storage_write_enable = 1'b1;
end else begin
data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0];
data_storage_write_enable = 1'b0;
usermem_data_out = data_storage_data_out;
end
end
// Configuration register access
// MEMORY MAP
// 0x00: Model number (read only)
// 0x01: Version (read only)
// 0x02: 4-bit I/O (lower 4 bits only)
// 0x03: 8-bit I/O
// 0x04: 16-bit I/O (upper 8 bits)
// 0x05: 16-bit I/O (lower 8 bits)
// 0x06: 7-segment LED digit 0 (read only)
// 0x07: 7-segment LED digit 1 (read only)
// 0x08: 7-segment LED digit 2 (read only)
// 0x09: 7-segment LED digit 3 (read only)
// 0x0a: User process register
// Bit 0: User processing start
// Bit 1: User processing done (read only)
// 0x20 - 0x3f: LCD data area
if (gpmc_wen_reg == 1'b0) begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_dina = gpmc_data_reg;
lcd_data_storage_wea = 1'b1;
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
2: begin
four_bit_switches = gpmc_data_reg[3:0];
end
3: begin
eight_bit_switches = gpmc_data_reg;
end
4: begin
sixteen_bit_io_out[15:8] = gpmc_data_reg;
end
5: begin
sixteen_bit_io_out[7:0] = gpmc_data_reg;
end
10: begin
userproc_start = gpmc_data_reg[0];
end
default: begin
// Do nothing
end
endcase
end
end else begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_wea = 1'b0;
gpmc_data_out = lcd_data_storage_douta;
end else begin
case (gpmc_address_reg[(RAM_ADDR_BITS-1):0])
0: begin
gpmc_data_out = 8'b01000010;
end
1: begin
gpmc_data_out = 8'b00000001;
end
2: begin
gpmc_data_out[7:4] = 0;
gpmc_data_out[3:0] = four_bit_leds;
end
3: begin
gpmc_data_out = eight_bit_leds;
end
4: begin
gpmc_data_out = sixteen_bit_io_in[15:8];
end
5: begin
gpmc_data_out = sixteen_bit_io_in[7:0];
end
6: begin
gpmc_data_out = led_display_bytes[0];
end
7: begin
gpmc_data_out = led_display_bytes[1];
end
8: begin
gpmc_data_out = led_display_bytes[2];
end
9: begin
gpmc_data_out = led_display_bytes[3];
end
10: begin
gpmc_data_out[0] = userproc_start;
gpmc_data_out[1] = userproc_done;
gpmc_data_out[7:2] = 0;
end
default: begin
gpmc_data_out = 0;
end
endcase
end
end
end
gpmc_data_driven = ((~gpmc_oen) && gpmc_wen);
end
endmodule

409
fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise
Unescape View File

@ -0,0 +1,409 @@
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<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ulab_debug_interface" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-01-09T21:09:55" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9842FBEA172DF24B03CC224838F538BE" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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fpga/common/remote_access.v → fpga/serial/common/remote_access.v
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fpga/xilinx/digilent/spartan_3/remote_access.v → fpga/serial/xilinx/digilent/spartan_3/remote_access.v
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fpga/xilinx/digilent/spartan_3e/remote_access.v → fpga/serial/xilinx/digilent/spartan_3e/remote_access.v
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fpga/xilinx/digilent/spartan_6/remote_access.v → fpga/serial/xilinx/digilent/spartan_6/remote_access.v
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fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v → fpga/serial/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
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