// *(gpmc + displacement + GPMC_CONFIG4) = 0x06020802; // Assert WE on fclk2, deassert WE on fclk6, assert OE on fclk2, deassert OE on fclk8
// *(gpmc + displacement + GPMC_CONFIG4) = 0x06020802; // Assert WE on fclk2, deassert WE on fclk6, assert OE on fclk2, deassert OE on fclk8
// *(gpmc + displacement + GPMC_CONFIG5) = 0x00060808; // Data valid on fclk 6, cycle time 8 fclks
// *(gpmc + displacement + GPMC_CONFIG5) = 0x00060808; // Data valid on fclk 6, cycle time 8 fclks
// 100MHz compatible SRAM device
// // 100MHz compatible SRAM device
*(gpmc+displacement+GPMC_CONFIG2)=0x00001000;// Assert CS on fclk0, deassert CS on fclk16
// *(gpmc + displacement + GPMC_CONFIG2) = 0x00001000; // Assert CS on fclk0, deassert CS on fclk16
// *(gpmc + displacement + GPMC_CONFIG3) = 0x00000400; // Assert ADV on fclk 0, deassert ADV on fclk 4
// *(gpmc + displacement + GPMC_CONFIG4) = 0x0c041004; // Assert WE on fclk4, deassert WE on fclk12, assert OE on fclk4, deassert OE on fclk16
// *(gpmc + displacement + GPMC_CONFIG5) = 0x000c1010; // Data valid on fclk 12, cycle time 16 fclks
// 50MHz compatible SRAM device
*(gpmc+displacement+GPMC_CONFIG2)=0x00001f00;// Assert CS on fclk0, deassert CS on fclk31
*(gpmc+displacement+GPMC_CONFIG3)=0x00000400;// Assert ADV on fclk 0, deassert ADV on fclk 4
*(gpmc+displacement+GPMC_CONFIG3)=0x00000400;// Assert ADV on fclk 0, deassert ADV on fclk 4
*(gpmc+displacement+GPMC_CONFIG4)=0x0c041004;// Assert WE on fclk4, deassert WE on fclk12, assert OE on fclk4, deassert OE on fclk16
*(gpmc+displacement+GPMC_CONFIG4)=0x1f041f04;// Assert WE on fclk4, deassert WE on fclk31, assert OE on fclk4, deassert OE on fclk31
*(gpmc+displacement+GPMC_CONFIG5)=0x000c1010;// Data valid on fclk 12, cycle time 16 fclks
*(gpmc+displacement+GPMC_CONFIG5)=0x00101f1f;// Data valid on fclk 16, cycle time 31 fclks
*(gpmc+displacement+GPMC_CONFIG6)=0x00000000;// No back to back cycle restrictions
*(gpmc+displacement+GPMC_CONFIG6)=0x00000000;// No back to back cycle restrictions
*(gpmc+displacement+GPMC_CONFIG7)=0x00000e50;// CS0: Set base address 0x10000000, 32MB region, and enable CS
*(gpmc+displacement+GPMC_CONFIG7)=0x00000e50;// CS0: Set base address 0x10000000, 32MB region, and enable CS
@ -180,6 +186,117 @@ static void io_setup(void)
// for (j=0;j<0x3ff; j++) {
// for (j=0;j<0x3ff; j++) {
// *(gpio + j) = j;
// *(gpio + j) = j;
// }
// }
// DEBUG ONLY
// Looping memory test
unsignedinttest_base=(MEMORY_SIZE/2);
unsignedinttest_length=(MEMORY_SIZE/2);
unsignedinttotal_errors;
unsignedcharerror_count[MEMORY_SIZE];
inti;
intloop;
unsignedintoverall_total_errors;
overall_total_errors=0;
for(loop=0;loop<10;loop++){
printf("Memory test loop %d\n",loop);
for(i=0;i<test_length;i++){
error_count[i]=0;
}
printf("\tTesting inversion pattern\n");
// Test with 0xaa
for(i=0;i<test_length;i++){
*(gpio_char+test_base+i)=0xaa;
}
for(i=0;i<test_length;i++){
unsignedcharresult=*(gpio_char+test_base+i);
if((result!=0xaa)){
error_count[i]=error_count[i]+1;
printf("\terror detected at offset 0x%02x (was 0x%02x, expected 0x%02x, second read attempt returned 0x%02x)\n",i,result,0xaa,(*(gpio_char+test_base+i)));
}
}
// Test with 0x55
for(i=0;i<test_length;i++){
*(gpio_char+test_base+i)=0x55;
}
for(i=0;i<test_length;i++){
unsignedcharresult=*(gpio_char+test_base+i);
if((result!=0x55)){
error_count[i]=error_count[i]+1;
printf("\terror detected at offset 0x%02x (was 0x%02x, expected 0x%02x, second read attempt returned 0x%02x)\n",i,result,0x55,(*(gpio_char+test_base+i)));
}
}
total_errors=0;
for(i=0;i<test_length;i++){
total_errors=total_errors+error_count[i];
if(error_count[i]>0){
printf("\t%d\terror(s) found at offset 0x%02x\n",error_count[i],i);
}
}
printf("\tTesting all ones/zeros\n");
// Test with 0xff
for(i=0;i<test_length;i++){
*(gpio_char+test_base+i)=0xff;
}
for(i=0;i<test_length;i++){
unsignedcharresult=*(gpio_char+test_base+i);
if((result!=0xff)){
error_count[i]=error_count[i]+1;
printf("\terror detected at offset 0x%02x (was 0x%02x, expected 0x%02x, second read attempt returned 0x%02x)\n",i,result,0xff,(*(gpio_char+test_base+i)));
}
}
// Test with 0x00
for(i=0;i<test_length;i++){
*(gpio_char+test_base+i)=0x00;
}
for(i=0;i<test_length;i++){
unsignedcharresult=*(gpio_char+test_base+i);
if((result!=0x00)){
error_count[i]=error_count[i]+1;
printf("\terror detected at offset 0x%02x (was 0x%02x, expected 0x%02x, second read attempt returned 0x%02x)\n",i,result,0x00,(*(gpio_char+test_base+i)));
}
}
printf("\tTesting alternating ones/zeros\n");
// Test with 0xff
for(i=0;i<test_length;i=i+2){
*(gpio_char+test_base+i)=0xff;
*(gpio_char+test_base+i+1)=0x00;
}
for(i=0;i<test_length;i=i+2){
unsignedcharresult;
result=*(gpio_char+test_base+i);
if((result!=0xff)){
error_count[i]=error_count[i]+1;
printf("\terror detected at offset 0x%02x (was 0x%02x, expected 0x%02x, second read attempt returned 0x%02x)\n",i,result,0xff,(*(gpio_char+test_base+i)));
}
result=*(gpio_char+test_base+i+1);
if((result!=0x00)){
error_count[i]=error_count[i]+1;
printf("\terror detected at offset 0x%02x (was 0x%02x, expected 0x%02x, second read attempt returned 0x%02x)\n",i,result,0x00,(*(gpio_char+test_base+i)));
}
}
total_errors=0;
for(i=0;i<test_length;i++){
total_errors=total_errors+error_count[i];
if(error_count[i]>0){
printf("\t%d\terror(s) found at offset 0x%02x\n",error_count[i],i);