`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////

module lcd_data_storage(
	input clka,
	input clkb,
	input [7:0] dina,
	input [7:0] dinb,
	input [4:0] addra,
	input [4:0] addrb,
	input wea,
	input web,
	output reg [7:0] douta,
	output reg [7:0] doutb);

	parameter RAM_WIDTH = 8;
	
	// Xilinx specific directive
	(* RAM_STYLE="BLOCK" *)
	
	reg [RAM_WIDTH-1:0] lcd_data_storage_ram [(2**5)-1:0];

	// Registered
	always @(posedge clka) begin
		douta <= lcd_data_storage_ram[addra];
		if (wea) begin
			lcd_data_storage_ram[addra] <= dina;
			douta <= dina;
		end
	end

	always @(posedge clkb) begin
		doutb <= lcd_data_storage_ram[addrb];
		if (web) begin
			lcd_data_storage_ram[addrb] <= dinb;
			doutb <= dinb;
		end
	end

// 	// Unregistered
// 	always @(posedge clka) begin
// 		if (wea) begin
// 			lcd_data_storage_ram[addra] <= dina;
// 		end
// 	end
// 	assign douta = lcd_data_storage_ram[addra];
// 
// 	always @(posedge clkb) begin
// 		if (web) begin
// 			lcd_data_storage_ram[addrb] <= dinb;
// 		end
// 	end
// 	assign doutb = lcd_data_storage_ram[addrb];

endmodule