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506 lines
17 KiB
506 lines
17 KiB
15 years ago
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// Register Declarations for Microchip 16F873 Processor
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//
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//
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// This header file was automatically generated by:
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//
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// inc2h.pl V1.5
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//
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// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
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//
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// SDCC is licensed under the GNU Public license (GPL) v2. Note that
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// this license covers the code to the compiler and other executables,
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// but explicitly does not cover any code or objects generated by sdcc.
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// We have not yet decided on a license for the run time libraries, but
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// it will not put any requirements on code linked against it. See:
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//
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// http://www.gnu.org/copyleft/gpl/html
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//
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// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
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//
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//
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#ifndef P16F873_H
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#define P16F873_H
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#define udata udata_shr
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#ifndef BIT_AT
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#define BIT_AT(base,bitno) sbit at ((base<<3)+bitno)
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#endif
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//
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// Register addresses.
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//
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#define INDF_ADDR 0x0000
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#define TMR0_ADDR 0x0001
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#define PCL_ADDR 0x0002
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#define STATUS_ADDR 0x0003
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#define FSR_ADDR 0x0004
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#define PORTA_ADDR 0x0005
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#define PORTB_ADDR 0x0006
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#define PORTC_ADDR 0x0007
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#define PCLATH_ADDR 0x000A
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#define INTCON_ADDR 0x000B
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#define PIR1_ADDR 0x000C
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#define PIR2_ADDR 0x000D
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#define TMR1L_ADDR 0x000E
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#define TMR1H_ADDR 0x000F
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#define T1CON_ADDR 0x0010
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#define TMR2_ADDR 0x0011
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#define T2CON_ADDR 0x0012
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#define SSPBUF_ADDR 0x0013
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#define SSPCON_ADDR 0x0014
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#define CCPR1L_ADDR 0x0015
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#define CCPR1H_ADDR 0x0016
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#define CCP1CON_ADDR 0x0017
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#define RCSTA_ADDR 0x0018
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#define TXREG_ADDR 0x0019
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#define RCREG_ADDR 0x001A
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#define CCPR2L_ADDR 0x001B
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#define CCPR2H_ADDR 0x001C
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#define CCP2CON_ADDR 0x001D
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#define ADRESH_ADDR 0x001E
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#define ADCON0_ADDR 0x001F
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#define OPTION_REG_ADDR 0x0081
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#define TRISA_ADDR 0x0085
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#define TRISB_ADDR 0x0086
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#define TRISC_ADDR 0x0087
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#define PIE1_ADDR 0x008C
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#define PIE2_ADDR 0x008D
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#define PCON_ADDR 0x008E
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#define SSPCON2_ADDR 0x0091
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#define PR2_ADDR 0x0092
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#define SSPADD_ADDR 0x0093
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#define SSPSTAT_ADDR 0x0094
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#define TXSTA_ADDR 0x0098
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#define SPBRG_ADDR 0x0099
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#define ADRESL_ADDR 0x009E
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#define ADCON1_ADDR 0x009F
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#define EEDATA_ADDR 0x010C
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#define EEADR_ADDR 0x010D
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#define EEDATH_ADDR 0x010E
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#define EEADRH_ADDR 0x010F
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#define EECON1_ADDR 0x018C
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#define EECON2_ADDR 0x018D
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//
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// Memory organization.
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//
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#pragma maxram 0x1FF
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#pragma memmap 0x0020 0x007f RAM 0x100
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#pragma memmap 0x00a0 0x00ff RAM 0x100
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#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
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#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
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#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
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#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
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#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
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#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
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#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
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#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
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#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
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#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
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#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
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#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
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#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
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#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
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#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
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#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
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#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
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#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
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#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
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#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
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#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
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#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
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#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
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#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
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#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
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#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
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#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
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#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
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#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
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#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
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#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
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#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
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#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
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#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
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#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
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#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
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#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
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#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
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#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
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#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
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#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
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#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
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#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
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#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
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#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
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#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
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#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
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#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
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#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
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#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
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#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
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// LIST
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// P16F873.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
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// NOLIST
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// This header file defines configurations, registers, and other useful bits of
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// information for the PIC16F873 microcontroller. These names are taken to match
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// the data sheets as closely as possible.
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// Note that the processor must be selected before this file is
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// included. The processor may be selected the following ways:
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// 1. Command line switch:
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// C:\ MPASM MYFILE.ASM /PIC16F873
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// 2. LIST directive in the source file
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// LIST P=PIC16F873
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// 3. Processor Type entry in the MPASM full-screen interface
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//==========================================================================
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//
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// Revision History
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//
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//==========================================================================
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//Rev: Date: Reason:
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//1.12 01/12/00 Changed some bit names, a register name, configuration bits
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// to match datasheet (DS30292B)
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//1.11 10/18/98 Changes to file registers to match updated DOS
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//1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1
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//1.00 08/07/98 Initial Release
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//==========================================================================
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//
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// Verify Processor
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//
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//==========================================================================
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// IFNDEF __16F873
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// MESSG "Processor-header file mismatch. Verify selected processor."
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// ENDIF
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//==========================================================================
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//
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// Register Definitions
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//
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//==========================================================================
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#define W 0x0000
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#define F 0x0001
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//----- Register Files------------------------------------------------------
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data at INDF_ADDR volatile char INDF;
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sfr at TMR0_ADDR TMR0;
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data at PCL_ADDR volatile char PCL;
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sfr at STATUS_ADDR STATUS;
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sfr at FSR_ADDR FSR;
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sfr at PORTA_ADDR PORTA;
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sfr at PORTB_ADDR PORTB;
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sfr at PORTC_ADDR PORTC;
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sfr at PCLATH_ADDR PCLATH;
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sfr at INTCON_ADDR INTCON;
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sfr at PIR1_ADDR PIR1;
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sfr at PIR2_ADDR PIR2;
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sfr at TMR1L_ADDR TMR1L;
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sfr at TMR1H_ADDR TMR1H;
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sfr at T1CON_ADDR T1CON;
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sfr at TMR2_ADDR TMR2;
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sfr at T2CON_ADDR T2CON;
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sfr at SSPBUF_ADDR SSPBUF;
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sfr at SSPCON_ADDR SSPCON;
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sfr at CCPR1L_ADDR CCPR1L;
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sfr at CCPR1H_ADDR CCPR1H;
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sfr at CCP1CON_ADDR CCP1CON;
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sfr at RCSTA_ADDR RCSTA;
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sfr at TXREG_ADDR TXREG;
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sfr at RCREG_ADDR RCREG;
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sfr at CCPR2L_ADDR CCPR2L;
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sfr at CCPR2H_ADDR CCPR2H;
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sfr at CCP2CON_ADDR CCP2CON;
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sfr at ADRESH_ADDR ADRESH;
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sfr at ADCON0_ADDR ADCON0;
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sfr at OPTION_REG_ADDR OPTION_REG;
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sfr at TRISA_ADDR TRISA;
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sfr at TRISB_ADDR TRISB;
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sfr at TRISC_ADDR TRISC;
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sfr at PIE1_ADDR PIE1;
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sfr at PIE2_ADDR PIE2;
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sfr at PCON_ADDR PCON;
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sfr at SSPCON2_ADDR SSPCON2;
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sfr at PR2_ADDR PR2;
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sfr at SSPADD_ADDR SSPADD;
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sfr at SSPSTAT_ADDR SSPSTAT;
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sfr at TXSTA_ADDR TXSTA;
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sfr at SPBRG_ADDR SPBRG;
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sfr at ADRESL_ADDR ADRESL;
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sfr at ADCON1_ADDR ADCON1;
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sfr at EEDATA_ADDR EEDATA;
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sfr at EEADR_ADDR EEADR;
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sfr at EEDATH_ADDR EEDATH;
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sfr at EEADRH_ADDR EEADRH;
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sfr at EECON1_ADDR EECON1;
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sfr at EECON2_ADDR EECON2;
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//----- STATUS Bits --------------------------------------------------------
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BIT_AT(STATUS_ADDR,7) IRP;
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BIT_AT(STATUS_ADDR,6) RP1;
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BIT_AT(STATUS_ADDR,5) RP0;
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BIT_AT(STATUS_ADDR,4) NOT_TO;
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BIT_AT(STATUS_ADDR,3) NOT_PD;
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BIT_AT(STATUS_ADDR,2) Z;
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BIT_AT(STATUS_ADDR,1) DC;
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BIT_AT(STATUS_ADDR,0) C;
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//----- INTCON Bits --------------------------------------------------------
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BIT_AT(INTCON_ADDR,7) GIE;
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BIT_AT(INTCON_ADDR,6) PEIE;
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BIT_AT(INTCON_ADDR,5) T0IE;
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BIT_AT(INTCON_ADDR,4) INTE;
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BIT_AT(INTCON_ADDR,3) RBIE;
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BIT_AT(INTCON_ADDR,2) T0IF;
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BIT_AT(INTCON_ADDR,1) INTF;
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BIT_AT(INTCON_ADDR,0) RBIF;
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//----- PIR1 Bits ----------------------------------------------------------
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BIT_AT(PIR1_ADDR,6) ADIF;
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BIT_AT(PIR1_ADDR,5) RCIF;
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BIT_AT(PIR1_ADDR,4) TXIF;
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BIT_AT(PIR1_ADDR,3) SSPIF;
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BIT_AT(PIR1_ADDR,2) CCP1IF;
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BIT_AT(PIR1_ADDR,1) TMR2IF;
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BIT_AT(PIR1_ADDR,0) TMR1IF;
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//----- PIR2 Bits ----------------------------------------------------------
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BIT_AT(PIR2_ADDR,6) CMIF;
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BIT_AT(PIR2_ADDR,4) EEIF;
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BIT_AT(PIR2_ADDR,3) BCLIF;
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BIT_AT(PIR2_ADDR,0) CCP2IF;
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//----- T1CON Bits ---------------------------------------------------------
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BIT_AT(T1CON_ADDR,5) T1CKPS1;
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BIT_AT(T1CON_ADDR,4) T1CKPS0;
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BIT_AT(T1CON_ADDR,3) T1OSCEN;
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BIT_AT(T1CON_ADDR,2) NOT_T1SYNC;
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BIT_AT(T1CON_ADDR,2) T1INSYNC; // Backward compatibility only
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BIT_AT(T1CON_ADDR,2) T1SYNC;
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BIT_AT(T1CON_ADDR,1) TMR1CS;
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BIT_AT(T1CON_ADDR,0) TMR1ON;
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//----- T2CON Bits ---------------------------------------------------------
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BIT_AT(T2CON_ADDR,6) TOUTPS3;
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BIT_AT(T2CON_ADDR,5) TOUTPS2;
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BIT_AT(T2CON_ADDR,4) TOUTPS1;
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BIT_AT(T2CON_ADDR,3) TOUTPS0;
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BIT_AT(T2CON_ADDR,2) TMR2ON;
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BIT_AT(T2CON_ADDR,1) T2CKPS1;
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BIT_AT(T2CON_ADDR,0) T2CKPS0;
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//----- SSPCON Bits --------------------------------------------------------
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BIT_AT(SSPCON_ADDR,7) WCOL;
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BIT_AT(SSPCON_ADDR,6) SSPOV;
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BIT_AT(SSPCON_ADDR,5) SSPEN;
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BIT_AT(SSPCON_ADDR,4) CKP;
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BIT_AT(SSPCON_ADDR,3) SSPM3;
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BIT_AT(SSPCON_ADDR,2) SSPM2;
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BIT_AT(SSPCON_ADDR,1) SSPM1;
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BIT_AT(SSPCON_ADDR,0) SSPM0;
|
||
|
|
|
||
|
|
//----- CCP1CON Bits -------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(CCP1CON_ADDR,5) CCP1X;
|
||
|
|
BIT_AT(CCP1CON_ADDR,4) CCP1Y;
|
||
|
|
BIT_AT(CCP1CON_ADDR,3) CCP1M3;
|
||
|
|
BIT_AT(CCP1CON_ADDR,2) CCP1M2;
|
||
|
|
BIT_AT(CCP1CON_ADDR,1) CCP1M1;
|
||
|
|
BIT_AT(CCP1CON_ADDR,0) CCP1M0;
|
||
|
|
|
||
|
|
//----- RCSTA Bits ---------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(RCSTA_ADDR,7) SPEN;
|
||
|
|
BIT_AT(RCSTA_ADDR,6) RX9;
|
||
|
|
BIT_AT(RCSTA_ADDR,6) RC9; // Backward compatibility only
|
||
|
|
BIT_AT(RCSTA_ADDR,6) NOT_RC8; // Backward compatibility only
|
||
|
|
BIT_AT(RCSTA_ADDR,6) RC8_9; // Backward compatibility only
|
||
|
|
BIT_AT(RCSTA_ADDR,5) SREN;
|
||
|
|
BIT_AT(RCSTA_ADDR,4) CREN;
|
||
|
|
BIT_AT(RCSTA_ADDR,3) ADDEN;
|
||
|
|
BIT_AT(RCSTA_ADDR,2) FERR;
|
||
|
|
BIT_AT(RCSTA_ADDR,1) OERR;
|
||
|
|
BIT_AT(RCSTA_ADDR,0) RX9D;
|
||
|
|
BIT_AT(RCSTA_ADDR,0) RCD8; // Backward compatibility only
|
||
|
|
|
||
|
|
//----- CCP2CON Bits -------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(CCP2CON_ADDR,5) CCP2X;
|
||
|
|
BIT_AT(CCP2CON_ADDR,4) CCP2Y;
|
||
|
|
BIT_AT(CCP2CON_ADDR,3) CCP2M3;
|
||
|
|
BIT_AT(CCP2CON_ADDR,2) CCP2M2;
|
||
|
|
BIT_AT(CCP2CON_ADDR,1) CCP2M1;
|
||
|
|
BIT_AT(CCP2CON_ADDR,0) CCP2M0;
|
||
|
|
|
||
|
|
//----- ADCON0 Bits --------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(ADCON0_ADDR,7) ADCS1;
|
||
|
|
BIT_AT(ADCON0_ADDR,6) ADCS0;
|
||
|
|
BIT_AT(ADCON0_ADDR,5) CHS2;
|
||
|
|
BIT_AT(ADCON0_ADDR,4) CHS1;
|
||
|
|
BIT_AT(ADCON0_ADDR,3) CHS0;
|
||
|
|
BIT_AT(ADCON0_ADDR,2) GO;
|
||
|
|
BIT_AT(ADCON0_ADDR,2) NOT_DONE;
|
||
|
|
BIT_AT(ADCON0_ADDR,2) GO_DONE;
|
||
|
|
BIT_AT(ADCON0_ADDR,0) ADON;
|
||
|
|
|
||
|
|
//----- OPTION_REG Bits ----------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(OPTION_REG_ADDR,7) NOT_RBPU;
|
||
|
|
BIT_AT(OPTION_REG_ADDR,6) INTEDG;
|
||
|
|
BIT_AT(OPTION_REG_ADDR,5) T0CS;
|
||
|
|
BIT_AT(OPTION_REG_ADDR,4) T0SE;
|
||
|
|
BIT_AT(OPTION_REG_ADDR,3) PSA;
|
||
|
|
BIT_AT(OPTION_REG_ADDR,2) PS2;
|
||
|
|
BIT_AT(OPTION_REG_ADDR,1) PS1;
|
||
|
|
BIT_AT(OPTION_REG_ADDR,0) PS0;
|
||
|
|
|
||
|
|
//----- PIE1 Bits ----------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(PIE1_ADDR,6) ADIE;
|
||
|
|
BIT_AT(PIE1_ADDR,5) RCIE;
|
||
|
|
BIT_AT(PIE1_ADDR,4) TXIE;
|
||
|
|
BIT_AT(PIE1_ADDR,3) SSPIE;
|
||
|
|
BIT_AT(PIE1_ADDR,2) CCP1IE;
|
||
|
|
BIT_AT(PIE1_ADDR,1) TMR2IE;
|
||
|
|
BIT_AT(PIE1_ADDR,0) TMR1IE;
|
||
|
|
|
||
|
|
//----- PIE2 Bits ----------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(PIE2_ADDR,4) EEIE;
|
||
|
|
BIT_AT(PIE2_ADDR,3) BCLIE;
|
||
|
|
BIT_AT(PIE2_ADDR,0) CCP2IE;
|
||
|
|
|
||
|
|
//----- PCON Bits ----------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(PCON_ADDR,1) NOT_POR;
|
||
|
|
BIT_AT(PCON_ADDR,0) NOT_BO;
|
||
|
|
BIT_AT(PCON_ADDR,0) NOT_BOR;
|
||
|
|
|
||
|
|
//----- SSPCON2 Bits --------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(SSPCON2_ADDR,7) GCEN;
|
||
|
|
BIT_AT(SSPCON2_ADDR,6) ACKSTAT;
|
||
|
|
BIT_AT(SSPCON2_ADDR,5) ACKDT;
|
||
|
|
BIT_AT(SSPCON2_ADDR,4) ACKEN;
|
||
|
|
BIT_AT(SSPCON2_ADDR,3) RCEN;
|
||
|
|
BIT_AT(SSPCON2_ADDR,2) PEN;
|
||
|
|
BIT_AT(SSPCON2_ADDR,1) RSEN;
|
||
|
|
BIT_AT(SSPCON2_ADDR,0) SEN;
|
||
|
|
|
||
|
|
//----- SSPSTAT Bits -------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(SSPSTAT_ADDR,7) SMP;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,6) CKE;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,5) D;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,5) I2C_DATA;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,5) NOT_A;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,5) NOT_ADDRESS;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,5) D_A;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,5) DATA_ADDRESS;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,4) P;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,4) I2C_STOP;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,3) S;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,3) I2C_START;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,2) R;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,2) I2C_READ;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,2) NOT_W;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,2) NOT_WRITE;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,2) R_W;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,2) READ_WRITE;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,1) UA;
|
||
|
|
BIT_AT(SSPSTAT_ADDR,0) BF;
|
||
|
|
|
||
|
|
//----- TXSTA Bits ---------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(TXSTA_ADDR,7) CSRC;
|
||
|
|
BIT_AT(TXSTA_ADDR,6) TX9;
|
||
|
|
BIT_AT(TXSTA_ADDR,6) NOT_TX8; // Backward compatibility only
|
||
|
|
BIT_AT(TXSTA_ADDR,6) TX8_9; // Backward compatibility only
|
||
|
|
BIT_AT(TXSTA_ADDR,5) TXEN;
|
||
|
|
BIT_AT(TXSTA_ADDR,4) SYNC;
|
||
|
|
BIT_AT(TXSTA_ADDR,2) BRGH;
|
||
|
|
BIT_AT(TXSTA_ADDR,1) TRMT;
|
||
|
|
BIT_AT(TXSTA_ADDR,0) TX9D;
|
||
|
|
BIT_AT(TXSTA_ADDR,0) TXD8; // Backward compatibility only
|
||
|
|
|
||
|
|
//----- ADCON1 Bits --------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(ADCON1_ADDR,7) ADFM;
|
||
|
|
BIT_AT(ADCON1_ADDR,3) PCFG3;
|
||
|
|
BIT_AT(ADCON1_ADDR,2) PCFG2;
|
||
|
|
BIT_AT(ADCON1_ADDR,1) PCFG1;
|
||
|
|
BIT_AT(ADCON1_ADDR,0) PCFG0;
|
||
|
|
|
||
|
|
//----- EECON1 Bits --------------------------------------------------------
|
||
|
|
|
||
|
|
BIT_AT(EECON1_ADDR,7) EEPGD;
|
||
|
|
BIT_AT(EECON1_ADDR,3) WRERR;
|
||
|
|
BIT_AT(EECON1_ADDR,2) WREN;
|
||
|
|
BIT_AT(EECON1_ADDR,1) WR;
|
||
|
|
BIT_AT(EECON1_ADDR,0) RD;
|
||
|
|
|
||
|
|
//==========================================================================
|
||
|
|
//
|
||
|
|
// RAM Definition
|
||
|
|
//
|
||
|
|
//==========================================================================
|
||
|
|
|
||
|
|
// __MAXRAM H'1FF'
|
||
|
|
// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
|
||
|
|
// __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
|
||
|
|
// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
|
||
|
|
|
||
|
|
//==========================================================================
|
||
|
|
//
|
||
|
|
// Configuration Bits
|
||
|
|
//
|
||
|
|
//==========================================================================
|
||
|
|
|
||
|
|
#define _CP_ALL 0x0FCF
|
||
|
|
#define _CP_HALF 0x1FDF
|
||
|
|
#define _CP_UPPER_256 0x2FEF
|
||
|
|
#define _CP_OFF 0x3FFF
|
||
|
|
#define _DEBUG_ON 0x37FF
|
||
|
|
#define _DEBUG_OFF 0x3FFF
|
||
|
|
#define _WRT_ENABLE_ON 0x3FFF
|
||
|
|
#define _WRT_ENABLE_OFF 0x3DFF
|
||
|
|
#define _CPD_ON 0x3EFF
|
||
|
|
#define _CPD_OFF 0x3FFF
|
||
|
|
#define _LVP_ON 0x3FFF
|
||
|
|
#define _LVP_OFF 0x3F7F
|
||
|
|
#define _BODEN_ON 0x3FFF
|
||
|
|
#define _BODEN_OFF 0x3FBF
|
||
|
|
#define _PWRTE_OFF 0x3FFF
|
||
|
|
#define _PWRTE_ON 0x3FF7
|
||
|
|
#define _WDT_ON 0x3FFF
|
||
|
|
#define _WDT_OFF 0x3FFB
|
||
|
|
#define _LP_OSC 0x3FFC
|
||
|
|
#define _XT_OSC 0x3FFD
|
||
|
|
#define _HS_OSC 0x3FFE
|
||
|
|
#define _RC_OSC 0x3FFF
|
||
|
|
|
||
|
|
// LIST
|
||
|
|
#endif
|