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@ -58,10 +58,15 @@ module main(
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output reg sixteen_bit_io_mode,
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input [3:0] sseg_mux,
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input [7:0] sseg_data);
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input [7:0] sseg_data,
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output userdevice_reset);
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parameter RAM_ADDR_BITS = 15;
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reg userdevice_reset_reg;
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assign userdevice_reset = ~userdevice_reset_reg;
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assign host_serial_txd = userlogic_serial_rxd;
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assign userlogic_serial_txd = host_serial_rxd;
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@ -394,6 +399,7 @@ module main(
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// 0x0b: Number of address bits of DSP RAM (read only)
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// 0x0c: User device control
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// Bit 0: User logic reset
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// Bit 1: User device reset
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// 0x20 - 0x3f: LCD data area
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// 0x4000 - 0x7fff: Logic analyzer data area (read only)
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if (gpmc_wen_reg == 1'b0) begin
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@ -420,6 +426,7 @@ module main(
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end
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12: begin
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userlogic_reset = gpmc_data_reg[0];
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userdevice_reset_reg = gpmc_data_reg[1];
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end
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default: begin
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// Do nothing
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@ -503,6 +510,7 @@ module main(
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end
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12: begin
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gpmc_data_out[0] = userlogic_reset;
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gpmc_data_out[1] = userdevice_reset_reg;
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gpmc_data_out[7:1] = 0;
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end
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default: begin
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