Minor tweaks to core remote FPGA file to eliminate Yosys warnings and reduce design sizemaster
Timothy Pearson
6 years ago
parent
e1e7c9e49d
commit
e1a4f6f17e
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# This file is part of the Universal Laboratory (uLab)
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#
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# © 2017 - 2019 Raptor Engineering, LLC
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# All Rights Reserved
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#
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# Licensed under the terms of the AGPL v3
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MAX_FPGA_ROUTE_PASSES = 100
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SOURCE_FILES = main.v remote_access.v
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# Default seed
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#ARACHNE_PNR_SEED = 1
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# Selected seed from fastest placement search
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# NOTE: Must be updated every time the Verilog source is modified, no matter how trivially!
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# Does not need to be updated if firmware program (C) sources are modified
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# 0 automatically uses the best placement result
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ARACHNE_PNR_SEED = 0
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#ARACHNE_PNR_SEED = 1
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YOSYS_ICE40_SIM_LIB = $(shell yosys-config --datdir/ice40/cells_sim.v)
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.PRECIOUS: control_fpga_%.int
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control_fpga_%.tmg: control_fpga_%.int control_fpga.pcf
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echo "Total path delay: inf ns (0.0 MHz)" > $@
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-icetime -tmd hx8k -p control_fpga.pcf -P ct256 $< > $@ 2>&1
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control_fpga_%.int: control_fpga.blif control_fpga.pcf
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echo "" > $@
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-arachne-pnr -s $* -d 8k -P ct256 -m $(MAX_FPGA_ROUTE_PASSES) -p control_fpga.pcf $< -o $@
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control_fpga.int: control_fpga_1.tmg control_fpga_2.tmg control_fpga_3.tmg control_fpga_4.tmg control_fpga_5.tmg control_fpga_6.tmg control_fpga_7.tmg control_fpga_8.tmg control_fpga_9.tmg \
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control_fpga_10.tmg control_fpga_11.tmg control_fpga_12.tmg control_fpga_13.tmg control_fpga_14.tmg control_fpga_15.tmg control_fpga_16.tmg control_fpga_17.tmg control_fpga_18.tmg control_fpga_19.tmg \
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control_fpga_20.tmg control_fpga_21.tmg control_fpga_22.tmg control_fpga_23.tmg control_fpga_24.tmg control_fpga_25.tmg control_fpga_26.tmg control_fpga_27.tmg control_fpga_28.tmg control_fpga_29.tmg \
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control_fpga_30.tmg control_fpga_31.tmg control_fpga_32.tmg control_fpga_33.tmg control_fpga_34.tmg control_fpga_35.tmg control_fpga_36.tmg control_fpga_37.tmg control_fpga_38.tmg control_fpga_39.tmg \
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control_fpga_40.tmg control_fpga_41.tmg control_fpga_42.tmg control_fpga_43.tmg control_fpga_44.tmg control_fpga_45.tmg control_fpga_46.tmg control_fpga_47.tmg control_fpga_48.tmg control_fpga_49.tmg \
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control_fpga_50.tmg control_fpga_51.tmg control_fpga_52.tmg control_fpga_53.tmg control_fpga_54.tmg control_fpga_55.tmg control_fpga_56.tmg control_fpga_57.tmg control_fpga_58.tmg control_fpga_59.tmg \
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control_fpga_60.tmg control_fpga_61.tmg control_fpga_62.tmg control_fpga_63.tmg control_fpga_64.tmg
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BEST_TRIAL=0; \
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BEST_TRIAL_RESULT=0; \
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for trial in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64; do \
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CURRENT_TRIAL_RESULT=$$(cat control_fpga_$${trial}.tmg | grep "Total path delay" | awk '{print $$6}' | sed 's/(//g'); \
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if [ "$$CURRENT_TRIAL_RESULT" != "" ]; then \
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echo "control_fpga_$${trial}.tmg : $$CURRENT_TRIAL_RESULT"; \
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COMPARISON_RESULT=$$(echo "$$CURRENT_TRIAL_RESULT > $$BEST_TRIAL_RESULT" | bc -l); \
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if [ $$COMPARISON_RESULT -eq 1 ]; then \
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BEST_TRIAL=control_fpga_$${trial}.tmg; \
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BEST_TRIAL_RESULT=$$CURRENT_TRIAL_RESULT; \
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fi; \
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fi; \
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done; \
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if [ "$$BEST_TRIAL_RESULT" -eq "0" ]; then \
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echo "Unable to determine fastest result. Selecting first run...."; \
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BEST_TRIAL=control_fpga_1.tmg; \
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BEST_TRIAL_RESULT=0; \
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fi; \
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echo "Fastest result: $$BEST_TRIAL : $$BEST_TRIAL_RESULT"; \
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cp `echo $$BEST_TRIAL | sed 's/\.tmg/\.int/g'` control_fpga.int; \
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cp $$BEST_TRIAL control_fpga.tmg
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ifneq ($(ARACHNE_PNR_SEED),0)
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cp control_fpga_$(ARACHNE_PNR_SEED).int control_fpga.int
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cp control_fpga_$(ARACHNE_PNR_SEED).tmg control_fpga.tmg
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endif
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cat control_fpga.tmg
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control_fpga.ex: control_fpga.int
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icebox_explain control_fpga.int > control_fpga.ex
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control_fpga.blif: $(SOURCE_FILES)
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yosys -l yosys.log -q -p "synth_ice40 -top control_fpga_top -blif control_fpga.blif" $(SOURCE_FILES)
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control_fpga.bin: control_fpga.int
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icepack control_fpga.int control_fpga.bin
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blank.rom:
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dd if=/dev/zero ibs=1k count=256 | tr "\000" "\377" > blank.rom
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control_fpga.rom: blank.rom control_fpga.bin
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cp blank.rom control_fpga.rom
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dd if=control_fpga.bin of=control_fpga.rom conv=notrunc
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control_fpga_test.vcd: $(SOURCE_FILES) testbench.v
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rm -f control_fpga_sim
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rm -f control_fpga.vcd
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/usr/bin/iverilog -DSIMULATION -o control_fpga_sim $(SOURCE_FILES) testbench.v
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./control_fpga_sim
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simulate: control_fpga_test.vcd
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simulate_view: control_fpga_test.vcd
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gtkwave control_fpga_test.vcd
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all: control_fpga.rom
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dump_toolchain_info:
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-@echo "================================================================================"
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-@echo "Base system:\t"
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-@echo -n "Architecture:\t"
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-@uname -m 2>/dev/null
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-@echo -n "gcc:\t\t"
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-@gcc -dumpversion 2>/dev/null
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-@echo -n "clang:\t\t"
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-@clang --version 2>/dev/null | head -n 1
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-@echo "\nFPGA toolchain:"
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-@echo -n "Icarus verilog:\t"
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-@iverilog -V 2>/dev/null | head -n 1
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-@echo -n "Yosys:\t\t"
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-@yosys -V 2>/dev/null
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-@echo -n "arachne-pnr:\t"
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-@arachne-pnr -v 2>/dev/null
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-@echo "================================================================================"
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test: control_fpga.bin
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iceprog -S control_fpga.bin
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flash: control_fpga.bin
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iceprog control_fpga.bin
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clean:
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rm -f control_fpga.blif control_fpga.ex control_fpga.int control_fpga.tmg control_fpga_*.int control_fpga_*.tmg control_fpga.bin yosys.log
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@ -0,0 +1,66 @@
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# This file is part of the Universal Laboratory (uLab)
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#
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# © 2017 - 2019 Raptor Engineering, LLC
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# All Rights Reserved
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#
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# Licensed under the terms of the AGPL v3
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# Main system clock
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set_io main_12_mhz_clock J3
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# Debug / GPIO connections
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set_io led_bank[7] C3
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set_io led_bank[6] B3
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set_io led_bank[5] C4
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set_io led_bank[4] C5
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set_io led_bank[3] A1
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set_io led_bank[2] A2
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set_io led_bank[1] B4
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set_io led_bank[0] B5
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# Guest FPGA interface
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set_io four_bit_output[3] C16
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set_io four_bit_output[2] D16
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set_io four_bit_output[1] E16
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set_io four_bit_output[0] F16
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set_io four_bit_input[3] B16
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set_io four_bit_input[2] D14
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set_io four_bit_input[1] D15
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set_io four_bit_input[0] E14
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set_io eight_bit_output[7] G16
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set_io eight_bit_output[6] H16
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set_io eight_bit_output[5] J15
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set_io eight_bit_output[4] G14
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set_io eight_bit_output[3] K14
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set_io eight_bit_output[2] K15
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set_io eight_bit_output[1] M16
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set_io eight_bit_output[0] N16
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set_io eight_bit_input[7] F15
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set_io eight_bit_input[6] G15
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set_io eight_bit_input[5] H14
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set_io eight_bit_input[4] F14
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set_io eight_bit_input[3] J14
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set_io eight_bit_input[2] K16
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set_io eight_bit_input[1] L16
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set_io eight_bit_input[0] M15
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set_io led_segment_bus[7] T1
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set_io led_segment_bus[6] R2
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set_io led_segment_bus[5] R3
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set_io led_segment_bus[4] T5
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set_io led_segment_bus[3] T6
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set_io led_segment_bus[2] T7
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set_io led_segment_bus[1] P8
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set_io led_segment_bus[0] T10
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set_io led_digit_select[3] T2
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set_io led_digit_select[2] T3
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set_io led_digit_select[1] R4
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set_io led_digit_select[0] R5
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# Serial interface
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set_io serial_input B10
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set_io serial_output B12
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@ -0,0 +1,98 @@
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// This file is part of the Universal Laboratory (uLab)
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//
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// © 2017 - 2019 Raptor Engineering, LLC
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// All Rights Reserved
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//
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// Licensed under the terms of the AGPL v3
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module control_fpga_top
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(
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// Input clock
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input wire main_12_mhz_clock,
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// Guest FPGA interface
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input wire [3:0] four_bit_output, // Output from the user program to the remote access module
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output wire [3:0] four_bit_input, // Input to the user program from the remote access module
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input wire [7:0] eight_bit_output, // Output from the user program to the remote access module
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output wire [7:0] eight_bit_input, // Input to the user program from the remote access module
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input wire [7:0] led_segment_bus,
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input wire [3:0] led_digit_select,
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// Serial interface
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input wire serial_input,
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output wire serial_output,
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// On-board diagnostic LEDs
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output wire [7:0] led_bank
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);
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parameter RAM_ADDR_BITS = 0;
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// Synthesize 50MHz clock from 12MHz clock
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wire main_50_mhz_clock;
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wire pll_locked;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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.DIVF(7'b1000010), // DIVF = 66
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.DIVQ(3'b100), // DIVQ = 4
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) system_pll (
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.LOCK(pll_locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(main_12_mhz_clock),
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.PLLOUTCORE(main_50_mhz_clock)
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);
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reg [7:0] diagnostic_led_data = 8'b0;
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wire [15:0] sixteen_bit_output; // Output from the user program to the remote access module
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wire [15:0] sixteen_bit_input; // Input to the user program from the remote access module
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wire [5:0] lcd_data_in_address;
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wire [7:0] lcd_data_in_data;
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wire lcd_data_in_enable;
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assign sixteen_bit_output = 16'b0; // Diable 16 bit input for now
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//assign led_bank = eight_bit_input; // Mirror input to the LEDs
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assign led_bank = diagnostic_led_data; // Show diagnostic data on LEDs
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reg [22:0] slow_clock_divider = 23'b0;
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wire slow_clock;
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reg [1:0] kr_state = 2'b0;
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always @(posedge main_12_mhz_clock) begin
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slow_clock_divider <= slow_clock_divider + 1;
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end
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assign slow_clock = slow_clock_divider[22];
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always @(posedge slow_clock) begin
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kr_state <= kr_state + 1;
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if (pll_locked) begin
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case (kr_state)
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0: diagnostic_led_data <= 8'b00011000;
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1: diagnostic_led_data <= 8'b00100100;
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2: diagnostic_led_data <= 8'b01000010;
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3: diagnostic_led_data <= 8'b10000001;
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endcase
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end else begin
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diagnostic_led_data <= 8'b0;
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end
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end
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assign lcd_data_in_enable = 1'b0; // Disable LCD I/O for now
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assign lcd_data_in_address = 6'b0; // Disable LCD I/O for now
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assign lcd_data_in_data = 8'b0; // Disable LCD I/O for now
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// Instantiate main remote access module
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remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_50_mhz_clock), .remote_access_4_bit_output(four_bit_output),
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.remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output),
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.remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output),
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.remote_access_16_bit_input(sixteen_bit_input),
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.serial_port_receiver(serial_input), .serial_port_transmitter(serial_output), .remote_access_input_enable(1'b0),
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.local_input(8'b0), .seize_serial_tx(1'b0), .serial_tx_data(8'b0), .serial_tx_strobe(1'b0),
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.lcd_data_in_address(lcd_data_in_address), .lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable),
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.led_segment_bus(led_segment_bus), .led_digit_select(led_digit_select));
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endmodule
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@ -0,0 +1 @@
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../../common/remote_access.v
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@ -0,0 +1,8 @@
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// This file is part of the Universal Laboratory (uLab)
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//
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// © 2017 - 2019 Raptor Engineering, LLC
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// All Rights Reserved
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//
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// Licensed under the terms of the AGPL v3
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// `define SYSTEM_HAS_SRAM 1
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@ -0,0 +1,8 @@
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// This file is part of the Universal Laboratory (uLab)
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//
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// © 2017 - 2019 Raptor Engineering, LLC
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// All Rights Reserved
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//
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// Licensed under the terms of the AGPL v3
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`define SYSTEM_HAS_SRAM 1
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@ -0,0 +1,8 @@
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// This file is part of the Universal Laboratory (uLab)
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//
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// © 2017 - 2019 Raptor Engineering, LLC
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// All Rights Reserved
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//
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// Licensed under the terms of the AGPL v3
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`define SYSTEM_HAS_SRAM 1
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@ -0,0 +1,8 @@
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// This file is part of the Universal Laboratory (uLab)
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//
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// © 2017 - 2019 Raptor Engineering, LLC
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// All Rights Reserved
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//
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// Licensed under the terms of the AGPL v3
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`define SYSTEM_HAS_SRAM 1
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