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70 lines
1.8 KiB
70 lines
1.8 KiB
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//
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// (c) 2014 Timothy Pearson, Raptor Engineering
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// Released into the Public Domain
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//
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//////////////////////////////////////////////////////////////////////////////////
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module logic_analyzer_data_storage(
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input clk,
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input [(RAM_WIDTH-1):0] dina,
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input [(RAM_WIDTH-1):0] dinb,
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input [(RAM_ADDR_BITS-1):0] addra,
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input [(RAM_ADDR_BITS-1):0] addrb,
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input wea,
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input web,
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output reg [(RAM_WIDTH-1):0] douta,
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output reg [(RAM_WIDTH-1):0] doutb);
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parameter RAM_ADDR_BITS = 11;
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parameter RAM_WIDTH = 64;
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// Xilinx specific directive
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(* RAM_STYLE="BLOCK" *)
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reg [RAM_WIDTH-1:0] logic_analyzer_data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
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// Initial RAM values for debugging
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integer index;
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initial begin
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for (index = 0; index < ((2**RAM_ADDR_BITS)-1); index = index + 2) begin
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logic_analyzer_data_storage_ram[index+0] = {(RAM_WIDTH/4){4'ha}};
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logic_analyzer_data_storage_ram[index+1] = {(RAM_WIDTH/4){4'h5}};
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end
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end
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// Registered
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always @(posedge clka) begin
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douta <= logic_analyzer_data_storage_ram[addra];
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if (wea) begin
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logic_analyzer_data_storage_ram[addra] <= dina;
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douta <= dina;
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end
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end
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always @(posedge clkb) begin
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doutb <= logic_analyzer_data_storage_ram[addrb];
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if (web) begin
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logic_analyzer_data_storage_ram[addrb] <= dinb;
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doutb <= dinb;
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end
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end
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// // Unregistered
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// always @(posedge clka) begin
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// if (wea) begin
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// logic_analyzer_data_storage_ram[addra] <= dina;
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// end
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// end
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// assign douta = logic_analyzer_data_storage_ram[addra];
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//
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// always @(posedge clkb) begin
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// if (web) begin
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// logic_analyzer_data_storage_ram[addrb] <= dinb;
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// end
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// end
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// assign doutb = logic_analyzer_data_storage_ram[addrb];
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endmodule
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