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142 lines
3.3 KiB
142 lines
3.3 KiB
/*
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* xsvftool-xpcu - An (X)SVF player for the Xilinx Platform Cable USB
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*
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* Copyright (C) 2011 RIEGL Research ForschungsGmbH
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* Copyright (C) 2011 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module top(
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clk,
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tck, tms, tdi, tdo, init, init_b,
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fd0, fd1, fd2, fd3, fd4, fd5, fd6, fd7,
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ctl0, ctl1, ctl2,
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pc0, pc1, pc2, pc3, pc4, pc5, pc6, pc7,
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pd0, pd1, pd2, pd3, pd4, pd5, pd6, pd7
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);
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// General Signal
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input clk;
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// JTAG Interface
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output tck, tms, tdi, init;
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input tdo, init_b;
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// GPIF Interface
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input fd0, fd1, fd2, fd3, fd4, fd5, fd6, fd7;
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input ctl0, ctl1, ctl2;
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// The entire PC and PD regs for various flags
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output pc0, pc1, pc2, pc3, pc4, pc5, pc6, pc7;
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input pd0, pd1, pd2, pd3, pd4, pd5, pd6, pd7;
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// simple direct i/o mappings
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assign pc3 = tdo;
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assign pc1 = init_b;
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assign init = pd2;
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// checksum
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wire chksum_rst, chksum_clk;
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reg [23:0] chksum_buffer;
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always @(posedge chksum_clk) begin
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if (chksum_rst)
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chksum_buffer <=
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`include "hardware_cksum_vl.inc"
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;
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else
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chksum_buffer <= chksum_buffer << 1;
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end
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assign chksum_rst = pd0;
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assign chksum_clk = pd1;
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assign pc2 = chksum_buffer[23];
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// main engine
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reg [3:0] sync;
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reg [7:0] lastbyte;
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reg go_exec0, go_exec1, set_sync, err;
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reg reg_tck, reg_tms, reg_tdi, reg_tdo, reg_tdo_en;
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always @(negedge clk) begin
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go_exec0 <= 0;
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go_exec1 <= 0;
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if (!ctl0) begin
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lastbyte <= { fd7, fd6, fd5, fd4, fd3, fd2, fd1, fd0 };
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go_exec0 <= 1;
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end
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if (!ctl1) begin
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lastbyte <= lastbyte >> 4;
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go_exec0 <= 1;
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end
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if (!ctl2) begin
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go_exec1 <= 1;
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end
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if (go_exec0) begin
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reg_tdo_en <= 0;
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if (set_sync) begin
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sync <= lastbyte[3:0];
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set_sync <= 0;
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end else
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if (lastbyte[3:0] == 0) begin
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/* NOP */
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end else
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if (lastbyte[3:0] == 1) begin
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/* Set sync signal in next insn */
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set_sync <= 1;
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end else
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if (lastbyte[3:1] == 1) begin
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/* reserved */
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end else
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if (lastbyte[3:2] == 1) begin
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/* transaction with or without TDO check */
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reg_tck <= 0;
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reg_tdo <= 'bx;
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reg_tms <= lastbyte[1];
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reg_tdi <= lastbyte[0];
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end else
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if (lastbyte[3] == 1) begin
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/* transaction with TDO check */
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reg_tck <= 0;
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reg_tdo <= lastbyte[2];
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reg_tms <= lastbyte[1];
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reg_tdi <= lastbyte[0];
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reg_tdo_en <= 1;
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end
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end
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if (go_exec1) begin
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reg_tck <= 1;
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if (reg_tdo_en && tdo != reg_tdo)
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err <= 1;
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end
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if (pd3) begin
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/* RESET ERR */
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err <= 0;
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end
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if (pd4) begin
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/* RESET SYNC */
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set_sync <= 0;
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sync <= 0;
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end
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end
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assign tck = reg_tck;
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assign tms = reg_tms;
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assign tdi = reg_tdi;
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assign pc7 = sync[3];
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assign pc6 = sync[2];
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assign pc5 = sync[1];
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assign pc4 = sync[0];
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assign pc0 = err;
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endmodule
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