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248 lines
7.6 KiB
248 lines
7.6 KiB
//
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// Copyright 2011 Xamarin Inc
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//
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#ifndef __MONO_ARM_VFP_CODEGEN_H__
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#define __MONO_ARM_VFP_CODEGEN_H__
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#include "arm-codegen.h"
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enum {
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/* VFP registers */
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ARM_VFP_F0,
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ARM_VFP_F1,
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ARM_VFP_F2,
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ARM_VFP_F3,
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ARM_VFP_F4,
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ARM_VFP_F5,
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ARM_VFP_F6,
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ARM_VFP_F7,
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ARM_VFP_F8,
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ARM_VFP_F9,
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ARM_VFP_F10,
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ARM_VFP_F11,
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ARM_VFP_F12,
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ARM_VFP_F13,
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ARM_VFP_F14,
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ARM_VFP_F15,
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ARM_VFP_F16,
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ARM_VFP_F17,
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ARM_VFP_F18,
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ARM_VFP_F19,
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ARM_VFP_F20,
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ARM_VFP_F21,
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ARM_VFP_F22,
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ARM_VFP_F23,
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ARM_VFP_F24,
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ARM_VFP_F25,
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ARM_VFP_F26,
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ARM_VFP_F27,
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ARM_VFP_F28,
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ARM_VFP_F29,
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ARM_VFP_F30,
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ARM_VFP_F31,
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ARM_VFP_D0 = ARM_VFP_F0,
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ARM_VFP_D1 = ARM_VFP_F2,
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ARM_VFP_D2 = ARM_VFP_F4,
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ARM_VFP_D3 = ARM_VFP_F6,
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ARM_VFP_D4 = ARM_VFP_F8,
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ARM_VFP_D5 = ARM_VFP_F10,
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ARM_VFP_D6 = ARM_VFP_F12,
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ARM_VFP_D7 = ARM_VFP_F14,
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ARM_VFP_D8 = ARM_VFP_F16,
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ARM_VFP_D9 = ARM_VFP_F18,
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ARM_VFP_D10 = ARM_VFP_F20,
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ARM_VFP_D11 = ARM_VFP_F22,
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ARM_VFP_D12 = ARM_VFP_F24,
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ARM_VFP_D13 = ARM_VFP_F26,
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ARM_VFP_D14 = ARM_VFP_F28,
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ARM_VFP_D15 = ARM_VFP_F30,
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ARM_VFP_COPROC_SINGLE = 10,
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ARM_VFP_COPROC_DOUBLE = 11,
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#define ARM_VFP_OP(p,q,r,s) (((p) << 23) | ((q) << 21) | ((r) << 20) | ((s) << 6))
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#define ARM_VFP_OP2(Fn,N) (ARM_VFP_OP (1,1,1,1) | ((Fn) << 16) | ((N) << 7))
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ARM_VFP_MUL = ARM_VFP_OP (0,1,0,0),
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ARM_VFP_NMUL = ARM_VFP_OP (0,1,0,1),
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ARM_VFP_ADD = ARM_VFP_OP (0,1,1,0),
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ARM_VFP_SUB = ARM_VFP_OP (0,1,1,1),
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ARM_VFP_DIV = ARM_VFP_OP (1,0,0,0),
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ARM_VFP_CPY = ARM_VFP_OP2 (0,0),
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ARM_VFP_ABS = ARM_VFP_OP2 (0,1),
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ARM_VFP_NEG = ARM_VFP_OP2 (1,0),
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ARM_VFP_SQRT = ARM_VFP_OP2 (1,1),
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ARM_VFP_CMP = ARM_VFP_OP2 (4,0),
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ARM_VFP_CMPE = ARM_VFP_OP2 (4,1),
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ARM_VFP_CMPZ = ARM_VFP_OP2 (5,0),
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ARM_VFP_CMPEZ = ARM_VFP_OP2 (5,1),
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ARM_VFP_CVT = ARM_VFP_OP2 (7,1),
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ARM_VFP_UITO = ARM_VFP_OP2 (8,0),
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ARM_VFP_SITO = ARM_VFP_OP2 (8,1),
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ARM_VFP_TOUI = ARM_VFP_OP2 (12,0),
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ARM_VFP_TOSI = ARM_VFP_OP2 (13,0),
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ARM_VFP_TOUIZ = ARM_VFP_OP2 (12,1),
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ARM_VFP_TOSIZ = ARM_VFP_OP2 (13,1),
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ARM_VFP_SID = 0,
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ARM_VFP_SCR = 1 << 1,
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ARM_VFP_EXC = 8 << 1
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};
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#define ARM_DEF_VFP_DYADIC(cond,cp,op,Fd,Fn,Fm) \
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(14 << 24) | \
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((cp) << 8) | \
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(op) | \
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(((Fd) >> 1) << 12) | \
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(((Fd) & 1) << 22) | \
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(((Fn) >> 1) << 16) | \
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(((Fn) & 1) << 7) | \
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(((Fm) >> 1) << 0) | \
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(((Fm) & 1) << 5) | \
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ARM_DEF_COND(cond)
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#define ARM_DEF_VFP_MONADIC(cond,cp,op,Fd,Fm) \
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(14 << 24) | \
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((cp) << 8) | \
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(op) | \
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(((Fd) >> 1) << 12) | \
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(((Fd) & 1) << 22) | \
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(((Fm) >> 1) << 0) | \
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(((Fm) & 1) << 5) | \
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ARM_DEF_COND(cond)
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#define ARM_DEF_VFP_LSF(cond,cp,post,ls,wback,basereg,Fd,offset) \
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((offset) >= 0? (offset)>>2: -(offset)>>2) | \
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(6 << 25) | \
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((cp) << 8) | \
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(((Fd) >> 1) << 12) | \
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(((Fd) & 1) << 22) | \
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((basereg) << 16) | \
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((ls) << 20) | \
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((wback) << 21) | \
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(((offset) >= 0) << 23) | \
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((wback) << 21) | \
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((post) << 24) | \
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ARM_DEF_COND(cond)
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#define ARM_DEF_VFP_CPT(cond,cp,op,L,Fn,Rd) \
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(14 << 24) | \
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(1 << 4) | \
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((cp) << 8) | \
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((op) << 21) | \
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((L) << 20) | \
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((Rd) << 12) | \
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(((Fn) >> 1) << 16) | \
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(((Fn) & 1) << 7) | \
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ARM_DEF_COND(cond)
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/* FP load and stores */
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#define ARM_FLDS_COND(p,freg,base,offset,cond) \
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ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_SINGLE,1,ARMOP_LDR,0,(base),(freg),(offset)))
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#define ARM_FLDS(p,freg,base,offset) \
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ARM_FLDS_COND(p,freg,base,offset,ARMCOND_AL)
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#define ARM_FLDD_COND(p,freg,base,offset,cond) \
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ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,1,ARMOP_LDR,0,(base),(freg),(offset)))
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#define ARM_FLDD(p,freg,base,offset) \
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ARM_FLDD_COND(p,freg,base,offset,ARMCOND_AL)
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#define ARM_FSTS_COND(p,freg,base,offset,cond) \
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ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_SINGLE,1,ARMOP_STR,0,(base),(freg),(offset)))
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#define ARM_FSTS(p,freg,base,offset) \
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ARM_FSTS_COND(p,freg,base,offset,ARMCOND_AL)
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#define ARM_FSTD_COND(p,freg,base,offset,cond) \
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ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,1,ARMOP_STR,0,(base),(freg),(offset)))
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#define ARM_FSTD(p,freg,base,offset) \
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ARM_FSTD_COND(p,freg,base,offset,ARMCOND_AL)
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#define ARM_FLDMD_COND(p,first_reg,nregs,base,cond) \
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ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,0,ARMOP_LDR,0,(base),(first_reg),((nregs) * 2) << 2))
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#define ARM_FLDMD(p,first_reg,nregs,base) \
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ARM_FLDMD_COND(p,first_reg,nregs,base,ARMCOND_AL)
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#define ARM_FSTMD_COND(p,first_reg,nregs,base,cond) \
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ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,0,ARMOP_STR,0,(base),(first_reg),((nregs) * 2) << 2))
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#define ARM_FSTMD(p,first_reg,nregs,base) \
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ARM_FSTMD_COND(p,first_reg,nregs,base,ARMCOND_AL)
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#include <mono/arch/arm/arm_vfpmacros.h>
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/* coprocessor register transfer */
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#define ARM_FMSR(p,freg,reg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,0,0,(freg),(reg)))
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#define ARM_FMRS(p,reg,freg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,0,1,(freg),(reg)))
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#define ARM_FMDLR(p,freg,reg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,0,0,(freg),(reg)))
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#define ARM_FMRDL(p,reg,freg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,0,1,(freg),(reg)))
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#define ARM_FMDHR(p,freg,reg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,1,0,(freg),(reg)))
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#define ARM_FMRDH(p,reg,freg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,1,1,(freg),(reg)))
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#define ARM_FMXR(p,freg,reg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,7,0,(freg),(reg)))
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#define ARM_FMRX(p,reg,fcreg) \
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ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,7,1,(fcreg),(reg)))
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#define ARM_FMSTAT(p) \
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ARM_FMRX((p),ARMREG_R15,ARM_VFP_SCR)
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#define ARM_DEF_MCRR(cond,cp,rn,rd,Fm,M) \
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((Fm) << 0) | \
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(1 << 4) | \
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((M) << 5) | \
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((cp) << 8) | \
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((rd) << 12) | \
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((rn) << 16) | \
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((2) << 21) | \
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(12 << 24) | \
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ARM_DEF_COND(cond)
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#define ARM_FMDRR(p,rd,rn,dm) \
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ARM_EMIT((p), ARM_DEF_MCRR(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,(rn),(rd),(dm) >> 1, (dm) & 1))
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#define ARM_DEF_FMRRD(cond,cp,rn,rd,Dm,D) \
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((Dm) << 0) | \
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(1 << 4) | \
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((cp) << 8) | \
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((rd) << 12) | \
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((rn) << 16) | \
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((0xc5) << 20) | \
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ARM_DEF_COND(cond)
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#define ARM_FMRRD(p,rd,rn,dm) \
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ARM_EMIT((p), ARM_DEF_FMRRD(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,(rn),(rd),(dm) >> 1, (dm) & 1))
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#define ARM_DEF_FUITOS(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xa) << 8) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
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#define ARM_FUITOS(p,dreg,sreg) \
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ARM_EMIT((p), ARM_DEF_FUITOS (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
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#define ARM_DEF_FUITOD(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xb) << 8) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
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#define ARM_FUITOD(p,dreg,sreg) \
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ARM_EMIT((p), ARM_DEF_FUITOD (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
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#define ARM_DEF_FSITOS(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xa) << 8) | ((1) << 7) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
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#define ARM_FSITOS(p,dreg,sreg) \
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ARM_EMIT((p), ARM_DEF_FSITOS (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
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#define ARM_DEF_FSITOD(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xb) << 8) | ((1) << 7) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
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#define ARM_FSITOD(p,dreg,sreg) \
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ARM_EMIT((p), ARM_DEF_FSITOD (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
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#endif /* __MONO_ARM_VFP_CODEGEN_H__ */
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