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<language name= "VHDL" version= "1.11" kateversion= "2.5" section= "Hardware" extensions= "*.vhdl;*.vhd" mimetype= "text/x-vhdl" author= "Rocky Scaletta (rocky@purdue.edu), Stefan Endrullis (stefan@endrullis.de), Florent Ouchet (outchy@users.sourceforge.net), Chris Higgs (chiggs.99@gmail.com), Jan Michel (jan@mueschelsoft.de)" >
<highlighting >
<list name= "keywordsToplevel" >
<item > file </item>
<!-- <item> package </item> -->
<item > library </item>
<item > use </item>
<!--
<item > entity </item>
<item > architecture </item>
<item > of </item>
<item > configuration </item>
-->
</list>
<list name= "keywords" >
<item > access </item>
<item > after </item>
<item > alias </item>
<item > all </item>
<item > array </item>
<item > assert </item>
<item > assume </item>
<item > assume_guarantee </item>
<item > attribute </item>
<item > begin </item>
<item > block </item>
<item > body </item>
<item > bus </item>
<item > component </item>
<item > constant </item>
<item > context </item>
<item > cover </item>
<item > default </item>
<item > disconnect </item>
<item > downto </item>
<item > end </item>
<item > exit </item>
<item > fairness </item>
<item > file </item>
<item > force </item>
<item > function </item>
<item > generate </item>
<item > generic </item>
<item > group </item>
<item > guarded </item>
<item > impure </item>
<item > inertial </item>
<item > is </item>
<item > label </item>
<item > linkage </item>
<item > literal </item>
<item > map </item>
<item > new </item>
<item > next </item>
<item > null </item>
<item > of </item>
<item > on </item>
<item > open </item>
<item > others </item>
<item > parameter </item>
<item > port </item>
<item > postponed </item>
<item > procedure </item>
<item > process </item>
<item > property </item>
<item > protected </item>
<item > pure </item>
<item > range </item>
<item > record </item>
<item > register </item>
<item > reject </item>
<item > release </item>
<item > report </item>
<item > return </item>
<item > select </item>
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<item > severity </item>
<item > signal </item>
<item > shared </item>
<item > strong </item>
<item > subtype </item>
<item > to </item>
<item > transport </item>
<item > type </item>
<item > unaffected </item>
<item > units </item>
<item > until </item>
<item > variable </item>
<item > vmode </item>
<item > vprop </item>
<item > vunit </item>
<item > wait </item>
<item > when </item>
<item > with </item>
<item > note </item>
<item > warning </item>
<item > error </item>
<item > failure </item>
<item > in </item>
<item > inout </item>
<item > out </item>
<item > buffer </item>
<item > and </item>
<item > abs </item>
<item > or </item>
<item > xor </item>
<item > xnor </item>
<item > not </item>
<item > mod </item>
<item > nand </item>
<item > nor </item>
<item > rem </item>
<item > rol </item>
<item > ror </item>
<item > sla </item>
<item > sra </item>
<item > sll </item>
<item > srl </item>
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<list name= "if" >
<item > if </item>
<item > else </item>
<item > elsif </item>
<item > then </item>
</list>
<list name= "forOrWhile" >
<item > loop </item>
</list>
<list name= "directions" >
<item > in </item>
<item > inout </item>
<item > out </item>
<item > buffer </item>
<item > linkage </item>
</list>
<list name= "signals" >
<item > signal </item>
<item > variable </item>
<item > constant </item>
<item > type </item>
</list>
<!-- <list name="logics">
<item > and </item>
<item > or </item>
<item > xor </item>
<item > not </item>
</list> -->
<list name= "range" >
<item > to </item>
<item > downto </item>
<item > others </item>
</list>
<list name= "case" >
<item > case </item>
<item > when </item>
</list>
<list name= "types" >
<item > bit </item>
<item > bit_vector </item>
<item > character </item>
<item > boolean </item>
<item > boolean_vector </item>
<item > integer </item>
<item > integer_vector </item>
<item > real </item>
<item > real_vector </item>
<item > time </item>
<item > time_vector </item>
<item > delay_length </item>
<item > string </item>
<item > severity_level </item>
<item > positive </item>
<item > natural </item>
<item > file_open_kind </item>
<item > file_open_status </item>
<item > signed </item>
<item > unsigned </item>
<item > unresolved_unsigned </item>
<item > unresolved_signed </item>
<item > line </item>
<item > text </item>
<item > side </item>
<item > width </item>
<item > std_logic </item>
<item > std_logic_vector </item>
<item > std_ulogic </item>
<item > std_ulogic_vector </item>
<item > x01 </item>
<item > x01z </item>
<item > ux01 </item>
<item > ux01z </item>
<item > qsim_state </item>
<item > qsim_state_vector </item>
<item > qsim_12state </item>
<item > qsim_12state_vector </item>
<item > qsim_strength </item>
<item > mux_bit </item>
<item > mux_vector </item>
<item > reg_bit </item>
<item > reg_vector </item>
<item > wor_bit </item>
<item > wor_vector </item>
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<IncludeRules context= "preDetection" />
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<StringDetect attribute= "Control" context= "entity" String= "entity" />
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String="&bos; (package\s+(&varname; )\s+is)&eos; "/>
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String="&bos; (package\s+body\s+(&varname; )\s+is)&eos; "/>
<!-- <StringDetect attribute="Control" context="arch_decl" String="package" />temporary -->
<keyword attribute= "Keyword" context= "#stay" String= "keywordsToplevel" />
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<IncludeRules context= "preDetection" />
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<IncludeRules context= "preDetection" />
<keyword attribute= "Signal" context= "signal" insensitive= "true" String= "signals" />
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<!-- ====generate =============== -->
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<IncludeRules context= "preDetection" />
<StringDetect attribute= "Control" context= "#stay" insensitive= "true"
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<RegExpr attribute= "Control" context= "#pop#pop" insensitive= "true" endRegion= "GenerateRegion"
String="&bos; end\s+generate(\s+&varname; )?\s*;"/>
<IncludeRules context= "detect_arch_parts" />
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<!-- ====process =============== -->
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<IncludeRules context= "preDetection" />
<RegExpr attribute= "Process" context= "#pop" insensitive= "true" dynamic= "true" endRegion= "RegionProcess"
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<!-- ====case =============== -->
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<IncludeRules context= "preDetection" />
<StringDetect attribute= "Keyword" context= "case2" insensitive= "true"
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<IncludeRules context= "preDetection" />
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<IncludeRules context= "proc_rules" />
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<IncludeRules context= "preDetection" />
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<IncludeRules context= "generalDetection" />
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<IncludeRules context= "preDetection" />
<RegExpr attribute= "Control" context= "#pop#pop" dynamic= "true" insensitive= "true" endRegion= "EntityRegion1"
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<RegExpr attribute= "Error" context= "#pop#pop" dynamic= "true" insensitive= "true" endRegion= "EntityRegion1"
String="&bos; end(\s+(entity|component))?(\s+&varname; )?\s*;" />
<RegExpr attribute= "Control" context= "#stay" String= "generic" />
<RegExpr attribute= "Control" context= "#stay" String= "port" />
<IncludeRules context= "generalDetection" />
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<!-- ====Basic Stuff =============== -->
<!-- basic rules -->
<context name= "preDetection" attribute= "Normal Text" lineEndContext= "#stay" >
<Detect2Chars attribute= "Comment" context= "comment" char= "-" char1= "-" />
<DetectChar attribute= "Vector" context= "string" char= """ />
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<DetectChar attribute= "Attribute" context= "attribute" char= "'" />
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<!-- general detection -->
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<keyword attribute= "Data Type" context= "#stay" String= "types" />
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<keyword attribute= "Keyword" context= "#stay" String= "keywords" />
<Int attribute= "Integer" context= "#stay" />
<HlCChar attribute= "Bit" context= "#stay" />
<DetectSpaces attribute= "Normal Text" context= "#stay" />
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<!-- other environments -->
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<context name= "string" attribute= "Vector" lineEndContext= "#stay" >
<DetectChar attribute= "Vector" context= "#pop" char= """ />
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<context name= "attribute" attribute= "Attribute" lineEndContext= "#pop" >
<DetectChar attribute= "Attribute" context= "quot in att" char= """ />
<DetectChar attribute= "Normal Text" context= "#pop" char= " " />
<DetectChar attribute= "Attribute" context= "#pop" char= "'" />
<AnyChar attribute= "Attribute" context= "#pop" String= "()=<>" />
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<context name= "quot in att" attribute= "Attribute" lineEndContext= "#stay" >
<DetectChar attribute= "Attribute" context= "#pop" char= """ />
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<context name= "signal" attribute= "Normal Text" lineEndContext= "#stay" >
<IncludeRules context= "preDetection" />
<DetectChar attribute= "Normal Text" context= "#pop" char= ";" endRegion= "sig" />
<IncludeRules context= "generalDetection" />
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<itemData name= "Redirection" defStyleNum= "dsKeyword" color= "#238" />
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<general >
<comments >
<comment name= "singleLine" start= "--" />
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<keywords casesensitive= "0" />
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