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1029 lines
40 KiB
1029 lines
40 KiB
<?xml version="1.0" encoding="UTF-8"?>
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<!--***********************************************************************-->
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<!-- $Id: systemverilog.xml 10 2009-06-25 03:41:39Z seanoboyle $ -->
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<!--***********************************************************************-->
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<!-- This program is free software: you can redistribute it and/or modify -->
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<!-- it under the terms of the GNU General Public License as published by -->
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<!-- the Free Software Foundation, either version 3 of the License, or -->
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<!-- (at your option) any later version. -->
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<!-- -->
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<!-- This program is distributed in the hope that it will be useful, -->
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<!-- but WITHOUT ANY WARRANTY; without even the implied warranty of -->
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<!-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -->
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<!-- GNU General Public License for more details. -->
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<!-- -->
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<!-- You should have received a copy of the GNU General Public License -->
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<!-- along with this program. If not, see <http://www.gnu.org/licenses/>.-->
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<!-- -->
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<!--***********************************************************************-->
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<!-- Title: SystemVerilog Language Keywords File for Kate Editor -->
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<!-- Description: This file contains the SV keywords defined in the -->
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<!-- IEEE1800-2009 Draft Standard in the format expected by -->
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<!-- the Kate Editor. -->
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<!-- -->
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<!-- Original Author: Sean O'Boyle -->
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<!-- Contact: seanoboyle@intelligentdv.com -->
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<!-- Company: Intelligent Design Verification -->
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<!-- Company URL: http://intelligentdv.com -->
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<!-- -->
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<!-- Download the most recent version here: -->
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<!-- http://intelligentdv.com/downloads -->
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<!-- -->
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<!-- File Bugs Here: http://bugs.intelligentdv.com -->
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<!-- Project: SyntaxFiles -->
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<!-- -->
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<!-- File: systemverilog.xml -->
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<!-- $LastChangedBy: seanoboyle $ -->
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<!-- $LastChangedDate: 2009-06-24 20:41:39 -0700 (Wed, 24 Jun 2009) $ -->
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<!-- $LastChangedRevision: 10 $ -->
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<!-- -->
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<!--***********************************************************************-->
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<!DOCTYPE language SYSTEM "language.dtd">
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<language name="SystemVerilog" version="2" kateversion="2.4" section="Hardware" extensions="*.sv;*.svh" mimetype="text/x-systemverilog-src" author="Sean O'Boyle (seanoboyle@intelligentdv.com)" license="GPL">
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<highlighting>
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|
<list name="key_deprecated">
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<item> defparam </item>
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|
<item> deassign </item>
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|
</list>
|
|
|
|
<list name="key_dpi">
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|
<item> DPI </item>
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|
<item> DPI-C </item>
|
|
<item> import </item>
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|
<item> export </item>
|
|
<item> context </item>
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|
</list>
|
|
|
|
<list name="key_assert">
|
|
<item> assert </item>
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|
<item> assume </item>
|
|
<item> cover </item>
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|
<item> expect </item>
|
|
<item> disable </item>
|
|
<item> iff </item>
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|
<item> binsof </item>
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|
<item> intersect </item>
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|
<item> first_match </item>
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|
<item> throughout </item>
|
|
<item> within </item>
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|
</list>
|
|
|
|
<list name="key_coverage">
|
|
<item> coverpoint </item>
|
|
<item> cross </item>
|
|
<item> wildcard </item>
|
|
<item> bins </item>
|
|
<item> ignore_bins </item>
|
|
<item> illegal_bins </item>
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|
</list>
|
|
|
|
<list name="key_generator">
|
|
<item> genvar </item>
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|
</list>
|
|
|
|
<list name="key_conditional">
|
|
<item> if </item>
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|
<item> else </item>
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|
<item> unique </item>
|
|
<item> priority </item>
|
|
<item> matches </item>
|
|
</list>
|
|
|
|
<list name="key_case">
|
|
<item> default </item>
|
|
</list>
|
|
|
|
<list name="key_loop">
|
|
<item> forever </item>
|
|
<item> repeat </item>
|
|
<item> while </item>
|
|
<item> for </item>
|
|
<item> do </item>
|
|
<item> foreach </item>
|
|
<item> break </item>
|
|
<item> continue </item>
|
|
<item> return </item>
|
|
</list>
|
|
|
|
<list name="key_specify">
|
|
<item> pulsestyle_onevent </item>
|
|
<item> pulsestyle_ondetect </item>
|
|
<item> noshowcancelled </item>
|
|
<item> showcancelled </item>
|
|
<item> ifnone </item>
|
|
</list>
|
|
|
|
<list name="key_procblock">
|
|
<item> initial </item>
|
|
<item> final </item>
|
|
<item> always </item>
|
|
<item> always_comb </item>
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|
<item> always_ff </item>
|
|
<item> always_latch </item>
|
|
</list>
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|
|
|
<list name="key_contassign">
|
|
<item> alias </item>
|
|
<item> assign </item>
|
|
<item> force </item>
|
|
<item> release </item>
|
|
</list>
|
|
|
|
<list name="key_event">
|
|
<item> posedge </item>
|
|
<item> negedge </item>
|
|
<item> edge </item>
|
|
<item> wait </item>
|
|
<item> wait_order </item>
|
|
</list>
|
|
|
|
<list name="key_time">
|
|
<item> timeunit </item>
|
|
<item> timeprecision </item>
|
|
<item> s </item>
|
|
<item> ms </item>
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|
<item> ns </item>
|
|
<item> us </item>
|
|
<item> ns </item>
|
|
<item> ps </item>
|
|
<item> fs </item>
|
|
<item> step </item>
|
|
</list>
|
|
|
|
<list name="key_class">
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|
<item> new </item>
|
|
<item> extends </item>
|
|
<item> this </item>
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|
<item> super </item>
|
|
<item> protected </item>
|
|
<item> local </item>
|
|
<item> rand </item>
|
|
<item> randc </item>
|
|
<item> bind </item>
|
|
</list>
|
|
|
|
<list name="key_constraint">
|
|
<item> constraint </item>
|
|
<item> solve </item>
|
|
<item> before </item>
|
|
<item> dist </item>
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|
<item> inside </item>
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|
<item> with </item>
|
|
</list>
|
|
|
|
<list name="key_methods">
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|
<item> virtual </item>
|
|
<item> pure </item>
|
|
<item> extern </item>
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|
<item> forkjoin </item>
|
|
</list>
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|
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|
<list name="key_config">
|
|
<item> design </item>
|
|
<item> instance </item>
|
|
<item> cell </item>
|
|
<item> liblist </item>
|
|
<item> use </item>
|
|
</list>
|
|
|
|
<list name="key_library">
|
|
<item> library </item>
|
|
<item> incdir </item>
|
|
<item> include </item>
|
|
</list>
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|
|
|
<list name="key_interface">
|
|
<item> modport </item>
|
|
</list>
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|
|
|
<list name="key_checker">
|
|
<item> sync_accept_on </item>
|
|
<item> reject_on </item>
|
|
<item> accept_on </item>
|
|
<item> sync_reject_on </item>
|
|
<item> restrict </item>
|
|
<item> let </item>
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|
<item> until </item>
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|
<item> until_with </item>
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|
<item> unique0 </item>
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|
<item> eventually </item>
|
|
<item> s_until </item>
|
|
<item> s_always </item>
|
|
<item> s_eventually </item>
|
|
<item> s_nexttime </item>
|
|
<item> s_until_with </item>
|
|
<item> global </item>
|
|
<item> untyped </item>
|
|
<item> implies </item>
|
|
<item> weak </item>
|
|
<item> strong </item>
|
|
<item> nexttime </item>
|
|
</list>
|
|
|
|
<list name="key_types">
|
|
<!-- parameters -->
|
|
<item> parameter </item>
|
|
<item> localparam </item>
|
|
<item> specparam </item>
|
|
<!-- port direction -->
|
|
<item> input </item>
|
|
<item> output </item>
|
|
<item> inout </item>
|
|
<item> ref </item>
|
|
<!-- integer atom type -->
|
|
<item> byte </item>
|
|
<item> shortint </item>
|
|
<item> int </item>
|
|
<item> integer </item>
|
|
<item> longint </item>
|
|
<item> time </item>
|
|
<!-- integer vector type -->
|
|
<item> bit </item>
|
|
<item> logic </item>
|
|
<item> reg </item>
|
|
<!-- net type -->
|
|
<item> supply0 </item>
|
|
<item> supply1 </item>
|
|
<item> tri </item>
|
|
<item> triand </item>
|
|
<item> trior </item>
|
|
<item> trireg </item>
|
|
<item> tri0 </item>
|
|
<item> tri1 </item>
|
|
<item> wire </item>
|
|
<item> uwire </item>
|
|
<item> wand </item>
|
|
<item> wor </item>
|
|
<!-- signing -->
|
|
<item> signed </item>
|
|
<item> unsigned </item>
|
|
<!-- noninteger type -->
|
|
<item> shortreal </item>
|
|
<item> real </item>
|
|
<item> realtime </item>
|
|
<!-- type reference -->
|
|
<item> type </item>
|
|
<item> void </item>
|
|
<!-- struct union -->
|
|
<item> struct </item>
|
|
<item> union </item>
|
|
<item> tagged </item>
|
|
<!-- modifier -->
|
|
<item> const </item>
|
|
<item> var </item>
|
|
<item> automatic </item>
|
|
<item> static </item>
|
|
<item> packed </item>
|
|
<item> vectored </item>
|
|
<item> scalared </item>
|
|
<!-- other types -->
|
|
<item> typedef </item>
|
|
<item> enum </item>
|
|
<item> string </item>
|
|
<item> chandle </item>
|
|
<item> event </item>
|
|
<!-- misc -->
|
|
<item> null </item>
|
|
</list>
|
|
|
|
<list name="key_preprocessor">
|
|
<item> `__FILE__ </item>
|
|
<item> `__LINE__ </item>
|
|
<item> `begin_keywords </item>
|
|
<item> `celldefine </item>
|
|
<item> `default_nettype </item>
|
|
<item> `define </item>
|
|
<item> `else </item>
|
|
<item> `elsif </item>
|
|
<item> `end_keywords </item>
|
|
<item> `endcelldefine </item>
|
|
<item> `endif </item>
|
|
<item> `ifdef </item>
|
|
<item> `ifndef </item>
|
|
<item> `include </item>
|
|
<item> `line </item>
|
|
<item> `nounconnected_drive </item>
|
|
<item> `pragma </item>
|
|
<item> `resetall </item>
|
|
<item> `timescale </item>
|
|
<item> `unconnected_drive </item>
|
|
<item> `undef </item>
|
|
<item> `undefineall </item>
|
|
</list>
|
|
|
|
<list name="key_system">
|
|
<item> $finish </item>
|
|
<item> $stop </item>
|
|
<item> $exit </item>
|
|
<item> $realtime </item>
|
|
<item> $stime </item>
|
|
<item> $time </item>
|
|
<item> $printtimescale </item>
|
|
<item> $timeformat </item>
|
|
<item> $bitstoreal </item>
|
|
<item> $realtobits </item>
|
|
<item> $bitstoshortreal </item>
|
|
<item> $shortrealtobits </item>
|
|
<item> $itor </item>
|
|
<item> $rtoi </item>
|
|
<item> $signed </item>
|
|
<item> $unsigned </item>
|
|
<item> $cast </item>
|
|
<item> $bits </item>
|
|
<item> $isunbounded </item>
|
|
<item> $typename </item>
|
|
<item> $unpacked_dimensions </item>
|
|
<item> $dimensions </item>
|
|
<item> $left </item>
|
|
<item> $right </item>
|
|
<item> $low </item>
|
|
<item> $high </item>
|
|
<item> $increment </item>
|
|
<item> $size </item>
|
|
<item> $clog2 </item>
|
|
<item> $asin </item>
|
|
<item> $ln </item>
|
|
<item> $acos </item>
|
|
<item> $log10 </item>
|
|
<item> $atan </item>
|
|
<item> $exp </item>
|
|
<item> $atan2 </item>
|
|
<item> $sqrt </item>
|
|
<item> $hypot </item>
|
|
<item> $pow </item>
|
|
<item> $sinh </item>
|
|
<item> $floor </item>
|
|
<item> $cosh </item>
|
|
<item> $ceil </item>
|
|
<item> $tanh </item>
|
|
<item> $sin </item>
|
|
<item> $asinh </item>
|
|
<item> $cos </item>
|
|
<item> $acosh </item>
|
|
<item> $tan </item>
|
|
<item> $atanh </item>
|
|
<item> $fatal </item>
|
|
<item> $error </item>
|
|
<item> $warning </item>
|
|
<item> $info </item>
|
|
<item> $fatal </item>
|
|
<item> $error </item>
|
|
<item> $warning </item>
|
|
<item> $info </item>
|
|
<item> $asserton </item>
|
|
<item> $assertoff </item>
|
|
<item> $assertkill </item>
|
|
<item> $assertpasson </item>
|
|
<item> $assertpassoff </item>
|
|
<item> $assertfailon </item>
|
|
<item> $assertfailoff </item>
|
|
<item> $assertnonvacuouson </item>
|
|
<item> $assertvacuousoff </item>
|
|
<item> $onehot </item>
|
|
<item> $onehot0 </item>
|
|
<item> $isunknown </item>
|
|
<item> $sampled </item>
|
|
<item> $rose </item>
|
|
<item> $fell </item>
|
|
<item> $stable </item>
|
|
<item> $changed </item>
|
|
<item> $past </item>
|
|
<item> $countones </item>
|
|
<item> $past_gclk </item>
|
|
<item> $rose_gclk </item>
|
|
<item> $fell_gclk </item>
|
|
<item> $stable_gclk </item>
|
|
<item> $changed_gclk </item>
|
|
<item> $future_gclk </item>
|
|
<item> $rising_gclk </item>
|
|
<item> $falling_gclk </item>
|
|
<item> $steady_gclk </item>
|
|
<item> $changing_gclk </item>
|
|
<item> $coverage_control </item>
|
|
<item> $coverage_get_max </item>
|
|
<item> $coverage_get </item>
|
|
<item> $coverage_merge </item>
|
|
<item> $coverage_save </item>
|
|
<item> $get_coverage </item>
|
|
<item> $set_coverage_db_name </item>
|
|
<item> $load_coverage_db </item>
|
|
<item> $random </item>
|
|
<item> $dist_chi_square </item>
|
|
<item> $dist_erlang </item>
|
|
<item> $dist_exponential </item>
|
|
<item> $dist_normal </item>
|
|
<item> $dist_poisson </item>
|
|
<item> $dist_t </item>
|
|
<item> $dist_uniform </item>
|
|
<item> $q_initialize </item>
|
|
<item> $q_add </item>
|
|
<item> $q_remove </item>
|
|
<item> $q_full </item>
|
|
<item> $q_exam </item>
|
|
<item> $async$and$array </item>
|
|
<item> $async$and$plane </item>
|
|
<item> $async$nand$array </item>
|
|
<item> $async$nand$plane </item>
|
|
<item> $async$or$array </item>
|
|
<item> $async$or$plane </item>
|
|
<item> $async$nor$array </item>
|
|
<item> $async$nor$plane </item>
|
|
<item> $sync$and$array </item>
|
|
<item> $sync$and$plane </item>
|
|
<item> $sync$nand$array </item>
|
|
<item> $sync$nand$plane </item>
|
|
<item> $sync$or$array </item>
|
|
<item> $sync$or$plane </item>
|
|
<item> $sync$nor$array </item>
|
|
<item> $sync$nor$plane </item>
|
|
<item> $system </item>
|
|
<item> $display </item>
|
|
<item> $write </item>
|
|
<item> $displayb </item>
|
|
<item> $writeb </item>
|
|
<item> $displayh </item>
|
|
<item> $writeh </item>
|
|
<item> $displayo </item>
|
|
<item> $writeo </item>
|
|
<item> $strobe </item>
|
|
<item> $monitor </item>
|
|
<item> $strobeb </item>
|
|
<item> $monitorb </item>
|
|
<item> $strobeh </item>
|
|
<item> $monitorh </item>
|
|
<item> $strobeo </item>
|
|
<item> $monitoro </item>
|
|
<item> $monitoroff </item>
|
|
<item> $monitoron </item>
|
|
<item> $fclose </item>
|
|
<item> $fopen </item>
|
|
<item> $fdisplay </item>
|
|
<item> $fwrite </item>
|
|
<item> $fdisplayb </item>
|
|
<item> $fwriteb </item>
|
|
<item> $fdisplayh </item>
|
|
<item> $fwriteh </item>
|
|
<item> $fdisplayo </item>
|
|
<item> $fwriteo </item>
|
|
<item> $fstrobe </item>
|
|
<item> $fmonitor </item>
|
|
<item> $fstrobeb </item>
|
|
<item> $fmonitorb </item>
|
|
<item> $fstrobeh </item>
|
|
<item> $fmonitorh </item>
|
|
<item> $fstrobeo </item>
|
|
<item> $fmonitoro </item>
|
|
<item> $swrite </item>
|
|
<item> $sformat </item>
|
|
<item> $swriteb </item>
|
|
<item> $sformatf </item>
|
|
<item> $swriteh </item>
|
|
<item> $fgetc </item>
|
|
<item> $swriteo </item>
|
|
<item> $ungetc </item>
|
|
<item> $fscanf </item>
|
|
<item> $fgets </item>
|
|
<item> $fread </item>
|
|
<item> $sscanf </item>
|
|
<item> $fseek </item>
|
|
<item> $rewind </item>
|
|
<item> $fflush </item>
|
|
<item> $ftell </item>
|
|
<item> $feof </item>
|
|
<item> $ferror </item>
|
|
<item> $readmemb </item>
|
|
<item> $readmemh </item>
|
|
<item> $writememb </item>
|
|
<item> $writememh </item>
|
|
<item> $test$plusargs </item>
|
|
<item> $value$plusargs </item>
|
|
<item> $dumpfile </item>
|
|
<item> $dumpvars </item>
|
|
<item> $dumpoff </item>
|
|
<item> $dumpon </item>
|
|
<item> $dumpall </item>
|
|
<item> $dumplimit </item>
|
|
<item> $dumpflush </item>
|
|
<item> $dumpports </item>
|
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<item> $dumpportsoff </item>
|
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<item> $dumpportson </item>
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<item> $dumpportsall </item>
|
|
<item> $dumpportslimit </item>
|
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<item> $dumpportsflush </item>
|
|
</list>
|
|
|
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<list name="key_gates">
|
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<item> pullup </item>
|
|
<item> pulldown </item>
|
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|
|
<item> rcmos </item>
|
|
<item> nmos </item>
|
|
<item> pmos </item>
|
|
<item> rnmos </item>
|
|
<item> rpmos </item>
|
|
<item> and </item>
|
|
<item> nand </item>
|
|
<item> or </item>
|
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<item> nor </item>
|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
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|
|
<item> tranif1 </item>
|
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|
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|
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|
|
<item> bufif1 </item>
|
|
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|
|
<item> notif1 </item>
|
|
</list>
|
|
|
|
<list name="key_strength">
|
|
<!-- drive strength -->
|
|
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|
|
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|
|
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|
|
<item> pull1 </item>
|
|
<item> weak0 </item>
|
|
<item> weak1 </item>
|
|
<item> highz0 </item>
|
|
<item> highz1 </item>
|
|
<!-- charge strength -->
|
|
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|
|
<item> medium </item>
|
|
<item> large </item>
|
|
</list>
|
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<list name="key_stdlib">
|
|
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|
|
<item> mailbox </item>
|
|
<item> semaphore </item>
|
|
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|
|
<item> get </item>
|
|
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|
|
<item> try_get </item>
|
|
<item> peek </item>
|
|
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|
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|
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|
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<item> self </item>
|
|
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|
|
<item> kill </item>
|
|
<item> await </item>
|
|
<item> suspend </item>
|
|
<item> resume </item>
|
|
<!-- Array -->
|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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<Detect2Chars attribute="Comment" context="Commentar 2" char="/" char1="*" beginRegion="Comment"/>
|
|
<RegExpr attribute="Comment" context="Outscoped intern" String="#\s*if" beginRegion="PP" firstNonSpace="true" />
|
|
<RegExpr attribute="Preprocessor" context="#pop" String="#\s*el(?:se|if)" firstNonSpace="true" />
|
|
<RegExpr attribute="Preprocessor" context="#pop" String="#\s*endif" endRegion="PP" firstNonSpace="true" />
|
|
</context>
|
|
|
|
<context attribute="Comment" lineEndContext="#stay" name="Outscoped intern">
|
|
<DetectSpaces />
|
|
<IncludeRules context="##Alerts" />
|
|
<DetectIdentifier />
|
|
<DetectChar attribute="String" context="String" char="""/>
|
|
<IncludeRules context="##Doxygen" />
|
|
<Detect2Chars attribute="Comment" context="Commentar 1" char="/" char1="/"/>
|
|
<Detect2Chars attribute="Comment" context="Commentar 2" char="/" char1="*" beginRegion="Comment"/>
|
|
<RegExpr attribute="Comment" context="Outscoped intern" String="#\s*if" beginRegion="PP" firstNonSpace="true" />
|
|
<RegExpr attribute="Comment" context="#pop" String="#\s*endif" endRegion="PP" firstNonSpace="true" />
|
|
</context>
|
|
|
|
<context attribute="Block Name" lineEndContext="#pop" name="Block Name">
|
|
<RegExpr attribute="Data Type Keyword" context="#pop" String="[^ ]+"/>
|
|
</context>
|
|
</contexts>
|
|
|
|
<itemDatas>
|
|
<itemData name="Normal Text" defStyleNum="dsNormal"/>
|
|
<itemData name="Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Block Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="DPI Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Assert Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Coverage Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Generator Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Confitional Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Case Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Loop Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Specify Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Process Block Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Continuous Assign Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Event Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Time Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Class Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Constraint Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Method Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Config Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Library Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Interface Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Checker Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Type Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Preprocessor Keyword" defStyleNum="dsOthers"/>
|
|
<itemData name="Preprocessor" defStyleNum="dsOthers"/>
|
|
<itemData name="System Task Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Data Type Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Drive/Charge Strength Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Gate Instantiation Keyword" defStyleNum="dsKeyword"/>
|
|
<itemData name="Data Type Keyword" defStyleNum="dsDataType"/>
|
|
<itemData name="Decimal" defStyleNum="dsBaseN"/>
|
|
<itemData name="Octal" defStyleNum="dsBaseN"/>
|
|
<itemData name="Hex" defStyleNum="dsBaseN"/>
|
|
<itemData name="Binary" defStyleNum="dsBaseN"/>
|
|
<itemData name="Float" defStyleNum="dsFloat"/>
|
|
<itemData name="String" defStyleNum="dsString"/>
|
|
<itemData name="String Char" defStyleNum="dsChar"/>
|
|
<itemData name="Comment" defStyleNum="dsComment"/>
|
|
<itemData name="Deprecated Keyword" defStyleNum="dsError"/>
|
|
<itemData name="Symbol" defStyleNum="dsNormal"/>
|
|
<itemData name="Preprocessor Keyword" defStyleNum="dsOthers"/>
|
|
<itemData name="Prep. Lib" defStyleNum="dsFloat"/>
|
|
<itemData name="PLI Task" defStyleNum="dsDataType"/>
|
|
<itemData name="System Task Keyword" defStyleNum="dsDataType"/>
|
|
<itemData name="Integer" defStyleNum="dsDecVal"/>
|
|
<itemData name="Delay" defStyleNum="dsBaseN"/>
|
|
<itemData name="Block Name" defStyleNum="dsDataType"/>
|
|
<itemData name="Drive/Charge Strength Keyword" defStyleNum="dsBaseN"/>
|
|
<itemData name="Gate Instantiation Keyword" defStyleNum="dsDataType"/>
|
|
<itemData name="Port Connection" defStyleNum="dsDataType"/>
|
|
<itemData name="Standard Library" defStyleNum="dsOthers"/>
|
|
</itemDatas>
|
|
</highlighting>
|
|
<general>
|
|
<comments>
|
|
<comment name="singleLine" start="//" />
|
|
<comment name="multiLine" start="/*" end="*/" region="Comment"/>
|
|
</comments>
|
|
<keywords casesensitive="1"/>
|
|
</general>
|
|
</language>
|