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# This file is part of the Universal Laboratory (uLab)
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#
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# © 2017 - 2019 Raptor Engineering, LLC
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# All Rights Reserved
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#
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# Licensed under the terms of the AGPL v3
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# Main system clock
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set_io main_12_mhz_clock J3
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# Debug / GPIO connections
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set_io led_bank[7] C3
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set_io led_bank[6] B3
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set_io led_bank[5] C4
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set_io led_bank[4] C5
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set_io led_bank[3] A1
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set_io led_bank[2] A2
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set_io led_bank[1] B4
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set_io led_bank[0] B5
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# Guest FPGA interface
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set_io guest_logic_reset A16
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set_io four_bit_output[3] C16
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set_io four_bit_output[2] D16
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set_io four_bit_output[1] E16
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set_io four_bit_output[0] F16
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set_io four_bit_input[3] B16
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set_io four_bit_input[2] D14
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set_io four_bit_input[1] D15
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set_io four_bit_input[0] E14
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set_io eight_bit_output[7] G16
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set_io eight_bit_output[6] H16
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set_io eight_bit_output[5] J15
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set_io eight_bit_output[4] G14
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set_io eight_bit_output[3] K14
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set_io eight_bit_output[2] K15
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set_io eight_bit_output[1] M16
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set_io eight_bit_output[0] N16
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set_io eight_bit_input[7] F15
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set_io eight_bit_input[6] G15
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set_io eight_bit_input[5] H14
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set_io eight_bit_input[4] F14
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set_io eight_bit_input[3] J14
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set_io eight_bit_input[2] K16
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set_io eight_bit_input[1] L16
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set_io eight_bit_input[0] M15
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set_io led_segment_bus[7] T1
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set_io led_segment_bus[6] R2
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set_io led_segment_bus[5] R3
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set_io led_segment_bus[4] T5
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set_io led_segment_bus[3] T6
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set_io led_segment_bus[2] T7
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set_io led_segment_bus[1] P8
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set_io led_segment_bus[0] T10
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set_io led_digit_select[3] T2
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set_io led_digit_select[2] T3
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set_io led_digit_select[1] R4
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set_io led_digit_select[0] R5
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# Serial interface
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set_io serial_input B10
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set_io serial_output B12
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