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Code Issues Releases Wiki Activity

Max out logic analyzer memory

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master
Timothy Pearson 11 years ago
parent 13aee3afa9
commit 061289c613
5 changed files with 102 additions and 17 deletions
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6
fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v
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@ -11,8 +11,8 @@ module logic_analyzer_data_storage(
input clkb,
input [63:0] dina,
input [63:0] dinb,
input [8:0] addra,
input [8:0] addrb,
input [10:0] addra,
input [10:0] addrb,
input wea,
input web,
output reg [63:0] douta,
@ -23,7 +23,7 @@ module logic_analyzer_data_storage(
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**9)-1:0];
reg [RAM_WIDTH-1:0] data_storage_ram [(2**11)-1:0];
always @(posedge clka) begin
douta <= data_storage_ram[addra];

26
fpga/gpmc/xilinx/common/main.v
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@ -40,6 +40,7 @@ module main(
output reg userproc_start,
input userproc_done,
output reg userlogic_reset,
input userlogic_clock,
input [3:0] four_bit_leds,
input [7:0] eight_bit_leds,
@ -114,19 +115,22 @@ module main(
.wea(lcd_data_storage_wea), .web(lcd_data_storage_web),
.douta(lcd_data_storage_douta), .doutb(lcd_data_storage_doutb));
wire logic_analyzer_clk;
logic_analyzer_clock_generator logic_analyzer_clock_generator(.clkin(clk), .clkout(logic_analyzer_clk));
wire logic_analyzer_data_storage_clka;
wire logic_analyzer_data_storage_clkb;
reg [63:0] logic_analyzer_data_storage_dina;
reg [63:0] logic_analyzer_data_storage_dinb;
reg [8:0] logic_analyzer_data_storage_addra;
reg [8:0] logic_analyzer_data_storage_addrb;
reg [10:0] logic_analyzer_data_storage_addra;
reg [10:0] logic_analyzer_data_storage_addrb;
reg logic_analyzer_data_storage_wea;
reg logic_analyzer_data_storage_web;
wire [63:0] logic_analyzer_data_storage_douta;
wire [63:0] logic_analyzer_data_storage_doutb;
assign logic_analyzer_data_storage_clka = clk;
assign logic_analyzer_data_storage_clkb = clk;
assign logic_analyzer_data_storage_clkb = logic_analyzer_clk;
logic_analyzer_data_storage logic_analyzer_data_storage(.clka(logic_analyzer_data_storage_clka), .clkb(logic_analyzer_data_storage_clkb),
.dina(logic_analyzer_data_storage_dina), .dinb(logic_analyzer_data_storage_dinb),
@ -243,8 +247,8 @@ module main(
reg logic_analyzer_trigger;
reg logic_analyzer_trigger_prev;
reg [9:0] logic_analyzer_address_counter;
always @(posedge clk) begin
reg [11:0] logic_analyzer_address_counter;
always @(posedge logic_analyzer_clk) begin
// Trigger
logic_analyzer_trigger = ~userlogic_reset; // Trigger on userlogic_reset falling edge
if ((logic_analyzer_trigger == 1) && (logic_analyzer_trigger_prev == 0)) begin
@ -252,7 +256,7 @@ module main(
end
// Data load
if (logic_analyzer_address_counter < 9'b100000000) begin
if (logic_analyzer_address_counter[11] == 1'b0) begin
logic_analyzer_data_storage_addrb = logic_analyzer_address_counter;
// Connect signals to logic analyzer
@ -266,8 +270,8 @@ module main(
logic_analyzer_data_storage_dinb[59:44] = usermem_address;
logic_analyzer_data_storage_dinb[60] = usermem_wen;
logic_analyzer_data_storage_dinb[61] = usermem_wait;
logic_analyzer_data_storage_dinb[62] = 1'b0;
logic_analyzer_data_storage_dinb[63] = 1'b0;
logic_analyzer_data_storage_dinb[62] = 1'b0; // UNUSED
logic_analyzer_data_storage_dinb[63] = userlogic_clock;
logic_analyzer_data_storage_web = 1'b1;
logic_analyzer_address_counter = logic_analyzer_address_counter + 1;
@ -383,7 +387,7 @@ module main(
// 0x0c: User device control
// Bit 0: User logic reset
// 0x20 - 0x3f: LCD data area
// 0x1000 - 0x1fff: Logic analyzer data area (read only)
// 0x4000 - 0x7fff: Logic analyzer data area (read only)
if (gpmc_wen_reg == 1'b0) begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
@ -419,8 +423,8 @@ module main(
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_wea = 1'b0;
gpmc_data_out = lcd_data_storage_douta;
end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):12] == 1) begin // Address range 0x1000 - 0x1fff
logic_analyzer_data_storage_addra = gpmc_address_reg[12:3];
end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):14] == 1) begin // Address range 0x4000 - 0x7fff
logic_analyzer_data_storage_addra = gpmc_address_reg[13:3];
logic_analyzer_data_storage_wea = 1'b0;
case (gpmc_address_reg[2:0])
0: begin

76
fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v
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@ -0,0 +1,76 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module logic_analyzer_clock_generator(
input clkin,
output clkout);
wire clk0;
wire clk2x;
reg reset;
assign clkout = clk0;
// assign clkout = clk2x;
// DCM_SP: Digital Clock Manager
// Spartan-6
// Xilinx HDL Language Template, version 14.7
DCM_SP #(
.CLKDV_DIVIDE(2.0), // CLKDV divide value
// (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
.CLKFX_DIVIDE(1), // Divide value on CLKFX outputs - D - (1-32)
.CLKFX_MULTIPLY(4), // Multiply value on CLKFX outputs - M - (2-32)
.CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE)
.CLKIN_PERIOD(10.0), // Input clock period specified in nS
.CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE)
.CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X)
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
.DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
.DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
.DSS_MODE("NONE"), // Unsupported - Do not change value
.DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value
.FACTORY_JF(16'hc080), // Unsupported - Do not change value
.PHASE_SHIFT(0), // Amount of fixed phase shift (-255 to 255)
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
DCM_SP_inst (
.CLK0(clk0), // 1-bit output: 0 degree clock output
.CLK180(), // 1-bit output: 180 degree clock output
.CLK270(), // 1-bit output: 270 degree clock output
.CLK2X(clk2x), // 1-bit output: 2X clock frequency clock output
.CLK2X180(), // 1-bit output: 2X clock frequency, 180 degree clock output
.CLK90(), // 1-bit output: 90 degree clock output
.CLKDV(), // 1-bit output: Divided clock output
.CLKFX(), // 1-bit output: Digital Frequency Synthesizer output (DFS)
.CLKFX180(), // 1-bit output: 180 degree CLKFX output
.LOCKED(), // 1-bit output: DCM_SP Lock Output
.PSDONE(), // 1-bit output: Phase shift done output
.STATUS(), // 8-bit output: DCM_SP status output
.CLKFB(clk0), // 1-bit input: Clock feedback input
.CLKIN(clkin), // 1-bit input: Clock input
.DSSEN(1'b0), // 1-bit input: Unsupported, specify to GND.
.PSCLK(), // 1-bit input: Phase shift clock input
.PSEN(1'b0), // 1-bit input: Phase shift enable
.PSINCDEC(), // 1-bit input: Phase shift increment/decrement input
.RST(reset) // 1-bit input: Active high reset input
);
// End of DCM_SP_inst instantiation
reg [7:0] reset_counter = 8'b00000001;
always @(posedge clkin) begin
if (reset_counter[7] != 1'b1) begin
reset_counter = reset_counter << 1;
reset = 1'b1;
end else begin
reset = 1'b0;
end
end
endmodule

1
fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
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@ -41,6 +41,7 @@ NET "usermem_wait" LOC = "T18" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "userproc_start" LOC = "K16" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "userproc_done" LOC = "L13" | IOSTANDARD = "LVCMOS33";
NET "userlogic_reset" LOC = "E13" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "userlogic_clock" LOC = "F13" | IOSTANDARD = "LVCMOS33";
NET "usermem_data<0>" LOC = "V14" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
NET "usermem_data<1>" LOC = "T11" | SLEW = FAST | IOSTANDARD = "LVCMOS33";

10
fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise
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@ -17,23 +17,27 @@
<files>
<file xil_pn:name="data_storage.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="lcd_data_storage.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="logic_analyzer_data_storage.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
</files>
<properties>

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