6 Commits (256facf7d34b09ba5da23af652a3bccd69ffe8f1)

Author	SHA1	Message	Date
Timothy Pearson	eb6afe10e6	Add a several cycle "dead zone" to 7-segment decoder segment select lines to more accurately emulate real hardware	7 years ago
Timothy Pearson	894b7938b3	Correctly implement 7-segment display LED persistence	7 years ago
Timothy Pearson	cd7e1ea3b8	Add user logic reset support to serial version of FPGA control interface	7 years ago
Timothy Pearson	e1a4f6f17e	Add intial version of Lattice remote FPGA interface ... Minor tweaks to core remote FPGA file to eliminate Yosys warnings and reduce design size	7 years ago
Timothy Pearson	e1e7c9e49d	Modify FPGA interface license to AGPL v3	7 years ago
Timothy Pearson	04ab7c6632	Add initial GOMC compatible uLab debug system hardware design files	12 years ago