Timothy Pearson
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6ed57d34ca
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First pass of logic analyzer functionality (GPMC interface and server)
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11 years ago |
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Timothy Pearson
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1fbfe13066
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First pass of logic analyzer functionality (client and FPGA core)
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11 years ago |
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Timothy Pearson
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72e80dda8e
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Add ability to hard reset user device
Fix initial size of serial and terminal windows
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11 years ago |
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Timothy Pearson
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2dc576d25f
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Hard reset user device on connection and disconnection of FPGA viewer
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11 years ago |
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Timothy Pearson
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038275fcc0
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Add serial I/O to host FPGA
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11 years ago |
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Timothy Pearson
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dc91899c25
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Add initial version of a logic analyzer server
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11 years ago |
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Timothy Pearson
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061289c613
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Max out logic analyzer memory
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11 years ago |
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Timothy Pearson
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13aee3afa9
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Merge branch 'master' of http://scm.trinitydesktop.org/scm/git/remotelaboratory
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11 years ago |
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Timothy Pearson
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1eb48edeba
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Add logic analyzer block to control FPGA
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11 years ago |
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Timothy Pearson
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32b7b87d3d
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Lower the uLab FPGA viewer GPMC clock to reduce errors on prototype lashup
Add memory stress tests to GPMC test program
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11 years ago |
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Timothy Pearson
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0ffb793cb5
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Relayout the GUI to be more in line with expected norms
Add user logic reset signal
Stabilize data transfer
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11 years ago |
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Timothy Pearson
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37420cfb78
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Increase DSP memory size
Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline
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11 years ago |
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Timothy Pearson
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a4eb2fb6bf
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Move hardware design files to their correct locations
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11 years ago |
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Timothy Pearson
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04ab7c6632
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Add initial GOMC compatible uLab debug system hardware design files
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11 years ago |
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Timothy Pearson
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963b88fb0b
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Add initial GPMC test program and associated files for BeagleBone Black
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11 years ago |
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Timothy Pearson
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38c56c7c1f
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Add initial version of SVF player for Beaglebone Black
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11 years ago |
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Timothy Pearson
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26c1236cdc
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Fix prior commit
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11 years ago |
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Timothy Pearson
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5c2d024b38
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Fix progress bar not moving during DSP data reception
Fix syntax error in demo main.v file
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11 years ago |
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Timothy Pearson
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8ce60c7f52
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Fix prior commit
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11 years ago |
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Timothy Pearson
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f27e0f0184
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Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side
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11 years ago |
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Timothy Pearson
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8faa3da109
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Fix image distortion when certain greyscale values are utilized
Store last used values in FPGA viewer and programmer GUI for convenience on GUI restart
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11 years ago |
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Timothy Pearson
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ff484b9d9c
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Fix 7 segment display malfunction at low multiplexing rates
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11 years ago |
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Timothy Pearson
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7997af3f4f
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Fix 7-segment LED display and add sample driver for the same
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11 years ago |
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Timothy Pearson
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976f4c5dfe
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Use 10-pin headers for ulab debug interface serial port on Spartan 6
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12 years ago |
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Timothy Pearson
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3f00d517b8
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Add sample image processing module to Spartan 6 demo project
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12 years ago |
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Timothy Pearson
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401379667e
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Properly report device programming errors
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12 years ago |
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Timothy Pearson
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400d0abcff
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Avoid usage of TQTimer::singleShot in the FPGA viewer part
Repair "think-o" in the Spartan 6 block RAM HDL
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12 years ago |
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Timothy Pearson
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9d5b0368df
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Add sample design for Spartan 6 and ISE 14.4
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12 years ago |
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Timothy Pearson
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40acabc2bf
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Update remote debug module and clean up FPGA section of the source tree
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12 years ago |
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Timothy Pearson
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1e0e205356
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Add verified Xilinx programming script and device type extractor
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12 years ago |
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Timothy Pearson
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f1ead12600
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Minor cleanup
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12 years ago |
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Timothy Pearson
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f0c477eef4
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Add magic 64 bytes to S6 svf file
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12 years ago |
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Timothy Pearson
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d94bf35fe7
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Add initial untested support for Spartan 6 devices
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12 years ago |
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Timothy Pearson
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9c6d284d49
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Initial rpi jtag support
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12 years ago |
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Timothy Pearson
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7643298424
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Update makefiles
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12 years ago |
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Timothy Pearson
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d1b70f8018
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Add initial files for direct FPGA programming
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12 years ago |
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Timothy Pearson
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db7e77be8f
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Add public domain FPGA files for Xilinx s3/s3e
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13 years ago |
