Timothy Pearson
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1fbfe13066
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First pass of logic analyzer functionality (client and FPGA core)
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11 years ago |
|
Timothy Pearson
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72e80dda8e
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Add ability to hard reset user device
Fix initial size of serial and terminal windows
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11 years ago |
|
Timothy Pearson
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038275fcc0
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Add serial I/O to host FPGA
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11 years ago |
|
Timothy Pearson
|
061289c613
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Max out logic analyzer memory
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11 years ago |
|
Timothy Pearson
|
1eb48edeba
|
Add logic analyzer block to control FPGA
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11 years ago |
|
Timothy Pearson
|
0ffb793cb5
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Relayout the GUI to be more in line with expected norms
Add user logic reset signal
Stabilize data transfer
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11 years ago |
|
Timothy Pearson
|
37420cfb78
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Increase DSP memory size
Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline
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11 years ago |
|
Timothy Pearson
|
a4eb2fb6bf
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Move hardware design files to their correct locations
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11 years ago |
|
Timothy Pearson
|
04ab7c6632
|
Add initial GOMC compatible uLab debug system hardware design files
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11 years ago |
