Timothy Pearson
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eb6afe10e6
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Add a several cycle "dead zone" to 7-segment decoder segment select lines to more accurately emulate real hardware
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7 years ago |
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Timothy Pearson
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9db454faca
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Slow demo file 7-segment clock to a more reasonable KHz value
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7 years ago |
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Timothy Pearson
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d64d218d18
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Fix incorrect pin assignment for 7-segment LED display
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7 years ago |
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Timothy Pearson
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894b7938b3
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Correctly implement 7-segment display LED persistence
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7 years ago |
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Timothy Pearson
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1733ea93c9
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Enable remaining I/O busses on Lattice control FPGA
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7 years ago |
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Timothy Pearson
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f8f6ee88d8
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Add test program for Lattice guest FPGAs
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7 years ago |
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Timothy Pearson
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cd7e1ea3b8
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Add user logic reset support to serial version of FPGA control interface
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7 years ago |
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Timothy Pearson
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e1a4f6f17e
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Add intial version of Lattice remote FPGA interface
Minor tweaks to core remote FPGA file to eliminate Yosys warnings and reduce design size
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7 years ago |
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Timothy Pearson
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e1e7c9e49d
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Modify FPGA interface license to AGPL v3
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7 years ago |
Timothy Pearson
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04ab7c6632
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Add initial GOMC compatible uLab debug system hardware design files
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12 years ago |