6 Commits (256facf7d34b09ba5da23af652a3bccd69ffe8f1)

Author	SHA1	Message	Date
Timothy Pearson	9db454faca	Slow demo file 7-segment clock to a more reasonable KHz value	7 years ago
Timothy Pearson	d64d218d18	Fix incorrect pin assignment for 7-segment LED display	7 years ago
Timothy Pearson	1733ea93c9	Enable remaining I/O busses on Lattice control FPGA	7 years ago
Timothy Pearson	f8f6ee88d8	Add test program for Lattice guest FPGAs	7 years ago
Timothy Pearson	cd7e1ea3b8	Add user logic reset support to serial version of FPGA control interface	7 years ago
Timothy Pearson	e1a4f6f17e	Add intial version of Lattice remote FPGA interface ... Minor tweaks to core remote FPGA file to eliminate Yosys warnings and reduce design size	7 years ago